NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 138

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 57.
5.9
5.9.1
Intel
DS
138
®
6300ESB I/O Controller Hub
Data Frame Format (Sheet 2 of 2)
Real Time Clock (D31:F0)
RTC Overview
The Real Time Clock (RTC) module provides a battery backed-up date and time keeping
device with two banks of static RAM with 128 bytes each, although the first bank has
114 bytes for general purpose usage. Three interrupt features are available: time of
day alarm with once a second to once a month range, periodic rates of 122 µs to 500
ms, and end of update cycle notification. Seconds, minutes, hours, days, day of week,
month, and year are counted. Daylight savings compensation is optional. The hour is
represented in twelve or twenty-four hour format, and data may be represented in BCD
or binary format. The design is meant to be functionally compatible with the Motorola*
MS146818B. The time keeping comes from a 32.768 KHz oscillating source, which is
divided to achieve an update every second. The lower 14 bytes on the lower RAM block
has very specific functions. The first ten are for time and date information. The next
four (0Ah to 0Dh) are registers, which configure and report RTC functions. See
Table 290
The time and calendar data should match the data mode (BCD or binary) and hour
mode (12 or 24 hour) as selected in register B. It is up to the programmer to make
sure that data stored in these locations is within the reasonable values ranges and
represents a possible date and time. The exceptions to these ranges is to store a value
of C0-FFh in the alarm bytes to indicate a “do not care” situation. All alarm conditions
must match to trigger an Alarm Flag, which could trigger an alarm interrupt when
enabled. The SET bit must be one while programming these locations to avoid clashes
with an update cycle. Access to time and date information is done through the RAM
locations. When a RAM read from the ten time and date bytes is attempted during an
update cycle, the value read will not necessarily represent the true contents of those
locations. Any RAM writes under the same conditions will be ignored.
NOTE: SIU_SERIRQ Period 13 is used to transfer IRQ12.
Frame
Data
10
11
12
13
14
15
16
17
18
19
20
21
#
9
for more information.
PCI INTD#
Interrupt
PCI INTA#
PCI INTB#
PCI INTC#
IOCHCK#
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ8
IRQ9
Clocks Past
Frame
Start
26
29
32
35
38
41
44
47
50
53
56
59
62
Before Port 60h latch
Do not include in BM IDE interrupt logic.
Do not include in BM IDE interrupt logic.
Same as ISA IOCHCK# going active.
Ignored. IRQ8# may only be generated internally or on
ISA.
Ignored. IRQ13 may only be generated from FERR#.
Drive PIRQA#
Drive PIRQB#
Drive PIRQC#
Drive PIRQD#
Comment
Order Number: 300641-004US
Intel
®
6300ESB ICH—5
November 2007