NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 191

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.15.4.2 Power State Transitions
5.15.4.2.1 Partial and Slumber State Entry/Exit
5.15.4.2.2 Device D1, D3 States
5.15.4.2.3 Host Controller D3 state
5.15.4.3 SMI Trapping (APM)
November 2007
Order Number: 300641-004US
®
6300ESB ICH
The partial and slumber states save interface power when the interface is idle. It would
be most analogous to PCI CLKRUN# (in power savings, not in mechanism), where the
interface may have power saved while no commands are pending.
The SATA Controller defines PHY layer power management (as performed through
primitives) as a driver operation from the host side, and a device proprietary
mechanism on the device side. The SATA Controller will accept device transition types,
but will not issue any transitions as a host. All received requests from a SATA device
will be ACKed.
When an operation is performed to the SATA Controller such that it needs to use the
SATA cable, the controller must check whether the link is in the Partial or Slumber
states, and if so, must issue a COM_WAKE to bring the link back online. Similarly, the
SATA device must perform the same action.
These states are entered after some period of time when software has determined that
no commands will be sent to this device for some time. The mechanism for putting a
device in these states does not involve any work on the host controller, other then
sending commands over the interface to the device. The command most likely to be
used in ATA/ATAPI is the “STANDBY IMMEDIATE” command.
After the interface and device have been put into a low power state, the host controller
may be put into a low power state. This is performed through the PCI power
management registers in configuration space.
There are two very important aspects to note when using PCI power management.
When the controller is put into D3, it is assumed that software has properly shut down
the device and disabled the ports. Therefore, there is no need to sustain any values on
the port wires. The interface will be treated as though no device is present on the
cable, and power will be minimized.
Offset 48h, bits 3:0 in the power management I/O space contain control for generating
SMI# on accesses to the IDE I/O spaces. These bits map to the legacy ranges only
(1f0-1f7h, 3f6h, 170-177h, and 376h). When the SATA controller is in legacy mode and
is using these addresses, accesses to one of these ranges with the appropriate bit set
will cause the cycle to not be forwarded to the SATA controller, and an SMI# is
generated.
To block accesses to the native IDE ranges, software must use the generic Power
Management control registers described in
CAh: MON[n]_TRP_RNG—I/O Monitor [4:7] Trap Range Register for Devices 4-7 (PM—
D31:F0)”.
1. When the power state is D3, only accesses to configuration space are allowed. Any
2. When the power state is D3, no interrupts may be generated, even when they are
attempt to access the memory or I/O spaces must result in master abort.
enabled. When an interrupt status bit is pending when the controller transitions to
D0, an interrupt may be generated.
Section 8.8.1.7, “Offset C4h, C6h, C8h,
Intel
®
6300ESB I/O Controller Hub
191
DS