NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 541

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

12—Intel
12.2.7
November 2007
Order Number: 300641-004US
Bits
Default Value:
7:0
Table 446. Offset 07h: Host_BLOCK_DB—Host Block Data Byte Register
Device:
®
Offset:
6300ESB ICH
Block Data (BDTA)
Offset 07h: Host_BLOCK_DB—Host Block Data
Byte Register
31
07h
00h
Name
This is either a register or a pointer into a 32-byte block
array, depending upon whether the E32B bit is set in the
Auxiliary Control register. When the E32B bit is cleared, this is
a register containing a byte of data to be sent on a block
write or read from on a block read.
When the E32B bit is set, reads and writes to this register are
used to access the 32-byte block data storage array. An
internal index pointer is used to address the array, which is
reset to ’0’ by reading the HCTL register (offset 02h). The
index pointer then increments automatically upon each
access to this register. The transfer of block data into (read)
or out of (write) this storage array during an SMBus
transaction always starts at index address 0.
When the E2B bit is set, for writes, software will write up to
32 bytes to this register as part of the setup for the
command. After the Host Controller has sent the Address,
Command, and Byte Count fields, it will send the bytes in the
SRAM pointed to by this register. After the byte count has
been exhausted, the controller will set the BYTE_DONE_STS
bit . See
When the E2B bit is cleared for writes, software will place a
single byte in this register. After the host controller has sent
the address, command, and byte count fields, it will send the
byte in this register. When there is more data to send,
software will write the next series of bytes to the SRAM
pointed to by this register and clear the BYTE_DONE_STS bit.
The controller will then send the next byte. During the time
between the last byte being transmitted to the next byte
being transmitted, the controller will insert wait states on the
interface.
When the E2B bit is set for reads, after receiving the byte
count into the Data0 register, the first series of data bytes go
into the SRAM pointed to by this register. When the byte
count has been exhausted or the 32-byte SRAM has been
filled, the controller will generate an SMI# or interrupt
(depending on configuration) and set the BYTE_DONE_STS
bit. Software will then read the data. During the time
between when the last byte is read from the SRAM to when
the BYTE_DONE_STS bit is cleared, the controller will insert
wait states on the interface.
Section
12.2.1,HST_STS-Host Status Register, bit 7.
Description
Attribute:
Function:
Size:
3
Read/Write
8-bit
Intel
®
6300ESB I/O Controller Hub
Access
R/W
541
DS