NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 70

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 13.
Intel
DS
70
®
6300ESB I/O Controller Hub
CPU Interface Signals (Sheet 2 of 2)
NOTES:
1. The CPU I/F signals (except RCIN#, A20GATE, and FERR#) are on a separate power well. This
2. RCIN# and A20GATE, and FERR# are on in the Core power well.
STPCLK#
A20GATE
IGNNE#
saves the external pull-up resistors that were needed on previous chipsets.
RCIN#
INIT#
Name
SMI#
INTR
NMI
Type
O
O
O
O
O
O
I
I
Ignore Numeric Error: This signal is connected to the ignore error
pin on the CPU. IGNNE# is only used when the Intel
coprocessor error reporting function is enabled in the General Control
Register (D31:F0:Offset D0.bit 5). When FERR# is active, indicating a
coprocessor error, a write to the Coprocessor Error Register (F0h)
causes the IGNNE# to be asserted. IGNNE# remains asserted until
FERR# is negated. If FERR# is not asserted when the Coprocessor
Error Register is written, the IGNNE# signal is not asserted.
Initialization: INIT# is asserted by the Intel
PCI clocks to reset the processor. The Intel
configured to support CPU BIST. In that case, INIT# will be active
when PXPCIRST# is active.
CPU Interrupt: INTR is asserted by the Intel
the processor that an interrupt request is pending and needs to be
serviced. It is an asynchronous output and normally driven low.
Non-Maskable Interrupt: NMI is used to force a non-Maskable
interrupt to the processor. The Intel
NMI when either SERR# or IOCHK# is asserted. The processor detects
an NMI when it detects a rising edge on NMI. NMI is reset by setting
the corresponding NMI source enable/disable bit in the NMI Status
and Control Register.
System Management Interrupt: SMI# is an active low output
synchronous to PCICLK. It is asserted by the Intel
response to one of many enabled hardware or software events.
Stop Clock Request: STPCLK# is an active low output synchronous
to PCICLK. It is asserted by the Intel
one of many hardware or software events. When the processor
samples STPCLK# asserted, it responds by stopping its internal clock.
This signal will not be connected to the processor in iA64 systems,
since the processor has no corresponding input signal.
Keyboard Controller Reset CPU: The keyboard controller may
generate INIT# to the processor. This saves the external OR gate with
the Intel
6300ESB ICH detects the assertion of this signal, INIT# is generated
for 16 PCI clocks.
Note that the Intel
transitions to the S1, S3, S4 and S5 states.
A20 Gate: From the keyboard controller. Acts as an alternative
method to force the A20M# signal active. Saves the external OR gate
needed with various other chipsets.
®
6300ESB ICH’s other sources of INIT#. When the Intel
®
6300ESB ICH will ignore RCIN# assertion during
Description
®
®
6300ESB ICH may generate an
6300ESB ICH in response to
®
Order Number: 300641-004US
®
6300ESB ICH may be
®
6300ESB ICH to signal
6300ESB ICH for 16
Intel
®
®
6300ESB ICH in
®
6300ESB ICH
6300ESB ICH—3
November 2007
®