NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 416

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 300. BUS_CYC_TRACK— Bus Cycle Tracker
8.9
8.9.1
Table 301. TCO I/O Register Map
Intel
DS
416
Bits
7:4
3:0
I/O Address:
®
6300ESB I/O Controller Hub
Lockable:
Device:
System Management TCO Registers
(D31:F0)
The TCO logic is accessed through registers mapped to the PCI configuration space
(Device 31:Function 0) and the system I/O space. For TCO PCI Configuration registers,
see LPC Device 31:Function 0 PCI Configuration registers.
TCO Register I/O Map
The TCO I/O registers reside in a 32-byte range pointed to by a TCOBASE value, which
is, ACPIBASE + 60h in the PCI config space. The following table shows the mapping of
the registers within that 32-byte range. Each register is described in the sections
below.
0Ch - 0Dh
04h - 05h
06h - 07h
08h - 09h
0Ah - 0Bh
31
PMBASE +4Eh
No
Name
Offset
00h
01h
02h
03h
0Eh
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Typ
e
Corresponds to the byte enables, as would be defined by the
PCI C/BE# signals on the PCI bus (even though it may not be
a real PCI cycle). The value is latched based on SMI# going
active.
Corresponds to the cycle type, as would be defined by the PCI
C/BE# signals on the PCI bus (even though it may not be a
real PCI cycle). The value is latched based on SMI# going
active.
TCO_RLD: TCO Timer Reload and Current Value
TCO_TMR: TCO Timer Initial Value
TCO_DAT_IN: TCO Data In
TCO_DAT_OUT: TCO Data Out
TCO1_STS: TCO Status
TCO2_STS: TCO Status
TCO1_CNT: TCO Control
TCO2_CNT: TCO Control
TCO_MESSAGE1, TCO_MESSAGE2: Used by BIOS to indicate POST/Boot
progress
TCO_WDSTATUS: Watchdog Status Register
Power Well:
Description
Attribute:
Function:
Register Name: Function
Size:
0
Read-Only
8-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
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