NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 435

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

9—Intel
IDE Controller Registers (D31:F1)
9.1
Table 322. PCI Configuration Map (IDE-D31:F1)
November 2007
Order Number: 300641-004US
NOTES:
1. See the Intel
2. The Intel
2C-2Dh
4A-4Bh
00-01h
02-03h
04-05h
06-07h
10-13h
14-17h
18-1Bh
1C-1Fh
20-23h
24-27h
40-41h
42-43h
Offset
2E-2Fh
0Bh
0Dh
08h
09h
0Ah
44h
48h
54h
latency timer.
3D
3C
®
Note: Registers that are not shown should be treated as Reserved (see
6300ESB ICH
®
IDE_CONFIG
SLV_IDETIM
Mnemonic
PCMD_BAR
SCMD_BAR
SDMA_CNT
PCNL_BAR
SCNL_BAR
IDE_SVID
6300ESB ICH IDE controller is not arbitrated as a PCI device, therefore it does not need a master
BM_BASE
SDMATIM
INTR_PN
IDE_SID
INTR_LN
IDE_TIM
ID_TIMS
PCI Configuration Registers (IDE—D31:F1)
Configuration Map”
registers may be locked.
®
CPBA
CMD
SCC
BCC
VID
DID
STS
RID
MLT
PI
6300ESB ICH Specification Update for the most up-to-date value of the Revision ID Register.
Vendor ID
Device ID
Command
Device Status
Revision ID
Programming Interface
Sub Class Code
Base Class Code
Master Latency Timer
Primary Command Block Base Address
Primary Control Block Base Address
Secondary Command Block Base Address
Secondary Control Block Base Address
Bus Master Base Address
IDE Command Posting Base Address
Subsystem Vendor ID
Subsystem ID
Interrupt Line
Interrupt Pin
Primary IDE Timing
Secondary IDE Timing
Slave IDE Timing
Synchronous DMA Control
Synchronous DMA Timing
IDE I/O Configuration
Register Name/Function
for details). All of the IDE registers are in the core well. None of the
00h See
00000001h
00000001h
00000001h
00000001h
00000001h
00000000h
Default
8086h
25A2h
0280h
0000h
0000h
0000h
00h
8Ah
01h
01h
00h
00h
00h
00h
01h
00h
00h
00h
Intel
Note 1
®
6300ESB I/O Controller Hub
Section 6.2, “PCI
R/Write-Once
R/Write-Once
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
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