NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 224

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.18.4
5.18.4.1 Periodic List Execution
5.18.4.1.1 Read Policies for Periodic DMA
Table 109. Read Policies for Periodic DMA
Intel
DS
224
®
6300ESB I/O Controller Hub
USB 2.0 Enhanced Host Controller DMA
The Intel
are, in order of priority on USB during each microframe:
The Intel
transaction at the beginning of a microframe, followed by any pending periodic traffic
for the current microframe. When there is time left in the microframe, then the EHC
performs any pending asynchronous traffic until the end of the microframe (EOF1).
Note that the debug port traffic is only presented on one port (Port #0), while the other
ports are idle during this time.
The following subsections describe the policies of the periodic and asynchronous DMA
engines.
The Periodic DMA engine contains buffering for two control structures (two
transactions). By implementing two entries, the EHC is able to pipeline the memory
accesses for the next transaction while executing the current transaction on the USB
ports. Note that a multiple-packet, High-Bandwidth transaction occupies one of these
buffer entries, which means that up to six 1-Kbyte data packets may be associated with
the two buffered control structures.
The Periodic DMA engine performs reads for the following structures.
Periodic Frame List
entry
iTD
siTD
qTD
Queue Head
Out Data
Frame Span
Transversal Node
1. USB 2.0 Debug Port (see
2. Periodic DMA engine
3. Asynchronous DMA engine
Memory Structure
®
®
6300ESB ICH USB 2.0 EHC implements three sources of USB packets. They
6300ESB ICH always performs any currently-pending debug port
(DWORDs)
Up to 257
Size
23
13
17
1
9
2
Section 5.18.11, “USB 2.0 EHCI Based Debug
The EHC reads the entry for each microframe. The
frame list is not internally cached across microframes.
Only the 64-bit addressing format is supported.
Only the 64-bit addressing format is supported.
Only the 64-bit addressing format is supported.
Only the 64-bit addressing format is supported.
The Intel
down into smaller aligned read requests based on the
setting of the Read Request Max Length field.
®
6300ESB ICH breaks large read requests
Comments
Order Number: 300641-004US
Intel
®
6300ESB ICH—5
November 2007
Port”)