NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 412

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.8.3.14 DEVACT_STS—Device Activity Status Register
Table 297. DEVACT_STS—Device Activity Status Register (Sheet 1 of 2)
Intel
DS
412
15:1
Bits
Default Value:
13
12
11
10
I/O Address:
4
9
®
6300ESB I/O Controller Hub
Lockable:
Note: This register is used in conjunction with the Periodic SMI# timer to detect any system
Note: Usage: Legacy only.
Device:
PIRQDH_ACT_STS
AUDIO_ACT_STS
ADLIB_ACT_STS
MIDI_ACT_STS
KBC_ACT_STS
activity for legacy power management.
Each bit indicates if the an access has occurred to the corresponding device’s trap
range, or for bits 6:9 if the corresponding PCI interrupt is active. Write 1 to the same
bit position to clear it. This register is used by APM power management software to see
if there has been system activity. The periodic SMI# timer indicates if it is the right
time to read the DEVTRAP_STS register.
Reserved
31
PMBASE +44h
0000h
No
Name
Reserved.
Ad-Lib.
0 = Indicates that there has been no access to this device’s I/
1 = This device’s I/O range has been accessed. Clear this bit
NOTE: This bit is no longer supported and will not be
KBC (60/64h).
0 = Indicates that there has been no access to this device’s I/
1 = This device’s I/O range has been accessed. Clear this bit
NOTE: If bit 7 of ETR1 (D31:F0, offset F4h, section 9.1.35) is
MIDI.
0 = Indicates that there has been no access to this device’s I/
1 = This device’s I/O range has been accessed. Clear this bit
NOTE: This bit is no longer supported and will not be
Audio (Sound Blaster “OR’d” with MSS).
0 = Indicates that there has been no access to this device’s I/
1 = This device’s I/O range has been accessed. Clear this bit
NOTE: This bit is no longer supported and will not be
PIRQ[D or H].
0 = The corresponding PCI interrupts have not been active.
1 = At least one of the corresponding PCI interrupts has been
O range.
by writing a 1 to the bit location.
O range.
by writing a 1 to the bit location.
O range.
by writing a 1 to the bit location.
O range.
by writing a 1 to the bit location.
active. Clear this bit by writing a 1 to the bit location.
validated.
set. Ports 60/64h accesses initiated from an external
PCI agent will not set this bit.
validated.
validated.
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write Clear
16-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/WC
R/WC
R/WC
R/WC
R/WC