NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 649

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18—Intel
18.3
November 2007
Order Number: 300641-004US
®
6300ESB ICH
transactions from PCI-X to the Hub Interface when the address is outside the range and
do not fall into the regular memory range (see
Address
granularity and alignment of 1 Mbyte.
This lower 32 bits of the range are defined by a 16-bit base register at offset 24h in
configuration space and a 16-bit limit register at offset 26h. The top 12 bits of each of
these registers correspond to bits [31:20] of the memory address. The low four bits are
hardwired to 1h, indicating 64-bit address support. The low 20 bits of the base address
are assumed to be all ‘0’s, which results in a natural alignment to a 1 Mbyte boundary.
The low 20 bits of the limit address are assumed to be all ‘1’s, which results in an
alignment to the top of a 1 Mbyte block.
The upper 32 bits of the range are defined by a 32-bit base register at offset 28h in
configuration space and a 32-bit limit register at offset 2Ch.
Setting the entire base (with upper 32 bits) to a value greater than that of the limit
turns off the memory range.
VGA Addressing
When a VGA-compatible device exists behind an Intel
enable bit in the bridge control register is set (offset 3 at 3E-3Fh). When set, the Intel
6300ESB ICH forwards all transactions addressing the VGA frame buffer memory and
VGA I/O registers from the Hub Interface to PCI-X, regardless of the values of the
Intel
ICH does not forward VGA frame buffer memory accesses to the Hub Interface
regardless of the values of the memory address ranges. However, the I/O enable and
memory enable bit in the command register must still be set. When cleared, the Intel
6300ESB ICH forwards transactions addressing the VGA frame buffer memory and VGA
I/O registers from the Hub Interface to PCI-X when the defined memory address
ranges enable forwarding. When cleared, accesses to the VGA frame buffer memory
are forwarded from PCI-X to the Hub Interface when the defined memory address
ranges enable forwarding. However, the master enable bit must still be set. The VGA I/
O addresses are never forwarded to the Hub Interface.
The VGA frame buffer consists of the following memory address range: 000A 0000h–
00B FFFFh.
The VGA I/O addresses consist of the I/O addresses 3B0h–3BBh and 3C0h–3DFh.
These I/O addresses are aliased every 1 Kbyte throughout the first 64 Kbyte of I/O
space. This means that address bits [9:0] (3B0h-3BBh and 3C0h-3DFh) are decoded,
[15:10] are not decoded and may be any value, and address bits [31:16] must be all
‘0’s.
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6300ESB ICH base and limit address registers. When set, the Intel
Registers”). This memory range supports 64-bit addressing and has a
Section 18.2.1, “Memory Base and Limit
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6300ESB ICH bridge, the VGA
Intel
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6300ESB I/O Controller Hub
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6300ESB
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DS
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