NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 31

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Contents—Intel
Figures
November 2007
Order Number: 300641-004US
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Workstation/PC Model.................................................................................................5
Low to Mid-Range Communication Appliance Model (Diskless) .......................................... 6
Value Server, Ultra-Dense Server and Low-End Server Blade ........................................... 7
Conceptual System Clock Diagram ............................................................................. 54
Power Plane Usage Model .......................................................................................... 80
Primary Device Status Register Error Reporting Logic .................................................... 93
Secondary Status Register Error Reporting Logic .......................................................... 94
NMI# Generation Logic ............................................................................................. 95
Typical Timing for LFRAME# .................................................................................... 101
Abort Mechanism ................................................................................................... 101
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DMA Request Assertion Through LDRQ# ................................................................... 107
Port 60 Read Clearing IRQ1 AND IRQ12 Latch............................................................ 120
Coprocessor Error Timing Diagram ........................................................................... 142
Latching Processor I/F Signals with STOPCLK#........................................................... 154
Physical Region Descriptor Table Entry...................................................................... 182
SATA Power States................................................................................................. 190
Transfer Descriptor ................................................................................................ 197
Example Queue Conditions ...................................................................................... 205
USB Data Encoding ................................................................................................ 208
USB Legacy Keyboard Flow Diagram ......................................................................... 219
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AC’97 2.2 Controller-Codec Connection ..................................................................... 261
AC-Link Protocol .................................................................................................... 262
AC-Link Powerdown Timing ..................................................................................... 270
SDIN Wake Signaling.............................................................................................. 271
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WDT Block Diagram ............................................................................................... 616
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Type ‘1’ to Type ‘0’ Translation ................................................................................ 651
SIU Block Diagram ................................................................................................ 704
Example UART Data Frame...................................................................................... 709
Start Frame Timing with Source Sampled a Low Pulse on IRQ1 .................................... 725
Stop Frame Timing with Host Using 17 SIU_SERIRQ Sampling Period ............................ 726
Ball Diagram (Top View - Left Side) .......................................................................... 771
Ball Diagram (Top View - Right Side) ........................................................................ 772
Mechanical Drawing................................................................................................ 773
PCI-X 3.3V Clock ................................................................................................... 813
Clock Uncertainty (PXPCLK[0:4]).............................................................................. 813
PCI-X Output Timing .............................................................................................. 814
PCI-X Input Timing ................................................................................................ 814
PCI-X RST# Timing for switching to PCI-X Mode Pull-ups ............................................. 815
Clock Timing ......................................................................................................... 815
Valid Delay from Rising Clock Edge........................................................................... 816
Setup and Hold Times............................................................................................. 816
Float Delay............................................................................................................ 816
Pulse Width ........................................................................................................... 816
Output Enable Delay............................................................................................... 817
IDE PIO Mode ........................................................................................................ 817
IDE Multiword DMA ................................................................................................ 818
Ultra ATA Mode (Drive Initiating a Burst Read)........................................................... 818
Ultra ATA Mode (Sustained Burst) ............................................................................ 819
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6300ESB ICH DMA Controller ......................................................................... 103
6300ESB ICH-USB Port Connections................................................................ 230
6300ESB ICH Based AC’97 Controller Connection to Companion Codec(s) ............ 260
6300ESB ICH Device Diagram ........................................................................ 277
6300ESB I/O Controller Hub Appearance to Software ........................................ 650
6300ESB ICH
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6300ESB I/O Controller Hub
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