NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 685

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18—Intel
18.7.3
18.7.4
18.7.5
18.7.5.1 Posted
November 2007
Order Number: 300641-004US
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6300ESB ICH
The Intel
Detection of 64-Bit Environment
The Intel
to signal that the bus is a 64-bit bus
Data Bus
For supplying data, the Intel
As a PCI master, when the Intel
PXACK64# asserted in the same clock that it detects PXDEVSEL# asserted, every data
phase then consists of 64 bits and eight byte enable bits.
On write transactions, when the Intel
asserted in the same clock that it detects PXDEVSEL# asserted, it redirects all data to
AD[31:0] and byte enables to C/BE#[3:0]. For 64-bit memory-write transactions that
end at an odd dWord boundary, the Intel
’1’, and drives random but stable data on PXAD[63:32].
On read transactions, the Intel
BE#[7:0]. It generates byte enables from the Hub Interface byte enables, with the
upper dWord driven on PXC/BE#[7:4]. When ACK64# is not sampled active with
PXDEVSEL# active, then the Intel
BE#[3:0].
The Intel
following conditions:
As a PCI target, the Intel
was not asserted by the initiator.
Write Transactions
Posted write forwarding is used for memory write and for memory write and invalidate
transactions. When the Intel
the Hub Interface, it asserts PXDEVSEL# and PXTRDY# in the same clock, provided
that enough buffer space is available in the posted data queue. The Intel
ICH adds no target wait states.
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The low 32 bits of data on PXAD[31:0]
The low four byte enable bits on PXC/BE#[3:0]
The high 32 bits of data on PXAD[63:32] (64-bit data phases only)
The high four byte enable bits on PXC/BE#[7:4] (64-bit data phases only)
The Intel
The Intel
The Intel
A 1-dWord or 2-dWord transaction is being performed.
When the address of the Hub Interface initiated transaction is not quad word
aligned.
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6300ESB ICH drives REQ64# low during PXPCIRST# on each PCI-X interface
6300ESB ICH decodes all PCI cycles in medium DEVSEL# timing.
6300ESB ICH does not assert REQ64# when initiating a transfer under the
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6300ESB ICH is initiating an I/O transaction.
6300ESB ICH is initiating a configuration transaction.
6300ESB ICH is initiating a special cycle transaction.
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6300ESB ICH does not assert PXACK64# when PXREQ64#
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6300ESB ICH drives the following in the data phase:
6300ESB ICH decodes a memory write transaction for
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6300ESB ICH drives eight bits of byte enables on PXC/
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6300ESB ICH drives PXREQ64# and detects
6300ESB ICH downshifts the all byte enables PXC/
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6300ESB ICH does not detect PXACK64#
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6300ESB ICH drives the byte enable bits to
Intel
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6300ESB I/O Controller Hub
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6300ESB
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