NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 140

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.9.1.5
Table 58.
Intel
DS
140
®
6300ESB I/O Controller Hub
Note: Both the GPI and SAFEMODE strap techniques to clear CMOS require multiple steps to
Clearing Battery-Backed RTC RAM
Clearing CMOS RAM in an Intel
jumper on RTCRST# or GPI, or using SAFEMODE strap. Implementations should not
attempt to clear CMOS by using a jumper to pull VccRTC low.
Using RTCRST# to clear CMOS:
A jumper on RTCRST# may be used to clear CMOS values, as well as reset to default,
the state of those configuration bits that reside in the RTC power well. When the
RTCRST# is strapped to ground, the RTC_PWR_STS bit (D31:F0:A4h bit 2) will be set
and those configuration bits in the RTC power well will be set to their default state.
BIOS may monitor the state of this bit, and manually clear the RTC CMOS array once
the system is booted. The normal position would cause RTCRST# to be pulled up
through a weak pull-up resistor.
state when RTCRST# is asserted.
Configuration Bits Reset By RTCRST# Assertion
Using a GPI to Clear CMOS:
A jumper on a GPI may also be used to clear CMOS values. BIOS would detect the
setting of this GPI on system boot-up, and manually clear the CMOS array.
Using the SAFEMODE Strap to Clear CMOS:
A jumper on AC_SDOUT (SAFEMODE strap) may also be used to clear CMOS values.
BIOS would detect the setting of the SAFE_MODE status bit (D31:F0: Offset D4h bit 2)
on system boot-up, and manually clear the CMOS array.
implement. The system is booted with the jumper in new position, then powered back
down. The jumper is replaced back to the normal position, then the system is rebooted
again. The RTCRST# jumper technique allows the jumper to be moved and then
replaced, all while the system is powered off. Then, once booted, the RTC_PWR_STS
may be detected in the set state.
AIE
AF
PWR_FLR
AFTERG3_EN
RTC_PWR_STS
PRBTNOR_STS
PME_EN
RI_EN
NEW_CENTURY_STS
INTRD_DET
TOP_SWAP
RTC_EN
BATLOW_EN
Bit Name
RTC Reg B
RTC Reg C
GEN_PMCON_3
GEN_PMCON_3
GEN_PMCON_3
PM1_STS
GPE0_EN
GPE0_EN
TCO1_STS
TCO2_STS
GEN_STS
PM1_EN
GPE0_EN
Default State
®
Table 58
6300ESB ICH-based platform may be done by using a
presents which bits are set to their default
I/O space
I/O space
D31:F0:A4h
D31:F0:A4h
D31:F0:A4h
PMBase + 00h
PMBase + 2Ah
PMBase + 2Ah
TCOBase + 04h
TCOBase + 06h
D31:F0:D4h
PMBase + 02h
PMBase + 2Ah
Register
Order Number: 300641-004US
Intel
Location
11
11
13
10
10
®
5
5
1
0
2
8
7
0
6300ESB ICH—5
November 2007
Bit(s)
0
0
0
0
1
0
0
0
0
0
0
0
0