NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 181

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
Table 81.
5.14.2.5 IORDY Masking
5.14.2.6 PIO 32-Bit IDE Data Port Accesses
5.14.2.7 PIO IDE Data Port Prefetching and Posting
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Shutdown latency is incurred after outstanding scheduled IDE data port transactions
(either a non-empty write post buffer or an outstanding read prefetch cycles) have
completed and before other transactions may proceed. It provides hold time on the
DA[2:0] and CSxx# lines with respect to the read and write strobes (DIOR# and
DIOW#). Shutdown latency is two PCI clocks in duration.
The IDE timings for various transaction types are shown in
Note that bit 2 (16-bit I/O recovery enable) of the ISA I/O Recovery Timer Register
does not add wait-states to IDE data port read accesses when any of the fast timing
modes are enabled.
IDE Transaction Timings (PCI Clocks)
The IORDY signal may be ignored and assumed asserted at the first IORDY Sample
Point (ISP) on a drive by drive basis through the IDETIM Register.
A 32-bit PCI transaction run to the IDE data address (01F0h primary, 0170h secondary)
results in two back to back 16-bit transactions to the IDE data port. The 32-bit data
port feature is enabled for all timings, not just enhanced timing. For compatible
timings, a shutdown and startup latency is incurred between the two 16-bit halves of
the IDE transaction. This ensures that the chip selects will be deasserted for at least
two PCI clocks between the two cycles.
The Intel
data to be posted to and prefetched from the IDE data ports.
Data pre fetching is initiated when a data port read occurs. The read prefetch
eliminates latency to the IDE data ports and allows them to be performed back to back
for the highest possible PIO data transfer rates. The first data port read of a sector is
called the demand read. Subsequent data port reads from the sector are called
prefetch reads. The demand read and all prefetch reads much be of the same size (16
or 32 bits).
Data posting is performed for writes to the IDE data ports. The transaction is completed
on the PCI bus after the data is received by the Intel
6300ESB ICH will then run the IDE cycle to transfer the data to the drive. When the
Intel
channel) IDE transaction occurs, that transaction will be stalled until all current data in
the write buffer is transferred to the drive.
Non-Data Port Compatible
®
IDE Transaction Type
Data Port Compatible
6300ESB ICH write buffer is non-empty and an unrelated (non-data or opposite
Fast Timing Mode
®
6300ESB ICH may be programmed through the IDETIM registers to allow
Latency
Startup
4
3
2
Point (ISP)
Sample
IORDY
11
6
2
®
6300ESB ICH. The Intel
Recovery Time
Table
Intel
(RCT)
®
22
14
81.
6300ESB I/O Controller Hub
1
Shutdown
Latency
®
2
2
2
181
DS