NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 384

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.8
8.8.1
Table 271. Power Management PCI Configuration Registers (D31:F0)
Intel
DS
384
®
6300ESB I/O Controller Hub
Power Management Registers (D31:F0)
The power management registers are distributed within the PCI Device 31: Function 0
space, as well as a separate I/O range. Each register is described below. Unless
otherwise indicate, bits are in the main (core) power well.
Bits not explicitly defined in each register are assumed to be reserved. When writing to
a reserved bit, the value should always be 0. Software should not attempt to use the
value read from a reserved bit, as it may not be consistently 1 or 0.
Power Management PCI Configuration Registers
(D31:F0)
Table 271
It includes only those registers dedicated for power management. Some of the
registers are only used for Legacy Power management schemes.
C4 - CAhh
B8 - BBh
40h-43h
Offset
C0h
CCh
44h
A0h
A2h
A4h
A8h
shows a small part of the configuration space for PCI Device 31: Function 0.
MON[n]_TRP_RNG
MON_TRP_MSK
GEN_PMCON_1
GEN_PMCON_2
GEN_PMCON_3
MON_FWD_EN
Mnemonic
ACPI_BASE
ACPI_CNTL
GPI_ROUT
Reserved
ACPI Base Address
ACPI Control
General Power Management
Configuration 1
General Power Management
Configuration 2
General Power Management
Configuration 3
GPI Route Control
I/O Monitor Forward Enable
I/O Monitor[4:7] Trap Range
I/O Monitor Trap Range Mask
Register Name/Function
Order Number: 300641-004US
Intel
00000001
00000000
Default
®
0000h
0000h
0000h
0Dh
6300ESB ICH—8
00h
00h
00h
00h
h
h
November 2007
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RW