NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 627

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NHE6300ESB S L7XJ

Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet

Specifications of NHE6300ESB S L7XJ

Lead Free Status / RoHS Status
Compliant
16—Intel
16.4.17 Offset F8 - FBh: Manufacturer’s ID
Table 552. Offset F8 - FBh: Manufacturer’s ID
16.4.18 Offset Base + 00h: Preload Value 1 Register
Table 553. Offset Base + 00h: Preload Value 1 Register
Preload Val ue 2 Regist er
November 2007
Order Number: 300641-004US
31:1
15:8
31:2
19:0
Bits
Bits
Default Value:
Default Value:
7:0
6
0
Lockable:
Lockable:
Device:
Device:
®
Preload_Value_1 [19:0]
Offset:
Offset:
6300ESB ICH
Manufacturer
Process/Dot
Reserved
Reserved
29
F8 - FBh
00000F66h
No
Name
29
Base + 00h
FFFFFh
No
Name
Reserved.
0Fh = Intel
66h
Reserved.
Use this register to hold the preload value for the WDT Timer.
The Value in the Preload Register is automatically transferred
into the 35-bit down-counter every time the WDT enters the
first stage.
NOTE: The value loaded into the preload register needs to be
Please refer to
for details on how to change the value of this register.
one less than the intended period, as the timer makes
use of zero-based counting (i.e., zero is counted as
part of the decrement).
Section 16.5.2, “Register Unlocking Sequence”
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
4
Read-Only
32-bit
Core
4
Read-Write
32-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/W
RO
RO
RO
RO
627
DS

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