NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 104

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.3.2
5.3.2.1
Table 37.
5.3.2.2
5.3.3
Intel
DS
104
®
6300ESB I/O Controller Hub
Channel Priority
For priority resolution, the DMA consists of two logical channel groups: channels 0–3
and channels 4–7. Each group may be in either fixed or rotate mode, as determined by
the DMA Command Register. See
information.
DMA I/O slaves normally assert their DREQ line to arbitrate for DMA service. However,
a software request for DMA service may be presented through each channel's DMA
Request Register. A software request is subject to the same prioritization as any
hardware request. Please see
Register”
information in the DMA I/O Register
Fixed Priority
The initial fixed priority structure is as described in
Fixed Priority
The fixed priority ordering is zero through seven. In this scheme, channel 0 has the
highest priority, and channel 7 has the lowest priority. Channels [3:0] of DMA-1 assume
the priority position of channel 4 in DMA-2, thus taking priority over channels 5, 6, and
7.
Rotating Priority
Rotation allows for “fairness” in priority resolution. The priority chain rotates so that the
last channel serviced is assigned the lowest priority in the channel group (0–3, 5–7).
Channels 0–3 rotate as a group of four. They are always placed between channel 5 and
channel 7 in the priority list.
Channel 5–7 rotate as part of a group of four. That is, channels (5–7) form the first
three positions in the rotation, while channel group (0–3) comprises the fourth position
in the arbitration.
Address Compatibility Mode
Whenever the DMA is operating, the addresses do not increment or decrement through
the High and Low Page Registers. Therefore, when a 24-bit address is 01FFFFh and
increments, the next address will be 010000h, not 020000h. Similarly, when a 24-bit
address is 020000h and decrements, the next address will be 02FFFFh, not 01FFFFh.
However, when the DMA is operating in 16 bit mode, the addresses still do not
increment or decrement through the High and Low Page Registers but the page
boundary is now 128K. Therefore, if a 24 bit address is 01FFFEh and increments, the
next address will be 000000h, not 010000h. Similarly, if a 24 bit address is 020000h
and decrements, the next address will be 03FFFEh, not 02FFFEh. This is compatible
with the 8237 and Page Register implementation used in the PC-AT. This mode is set
after CPURST is valid.
High priority.....Low priority
(0, 1, 2, 3)
for detailed register description for Request Register programming
(5, 6, 7)
Section 8.4.9, “OCW3—Operational Control Word 3
Section 8.2, “DMA I/O Registers”
(Section 8.2, “DMA I/O
Table
37.
Registers”).
Order Number: 300641-004US
Intel
for more
®
6300ESB ICH—5
November 2007