NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 180

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 80.
5.14.2.4 PIO IDE Timing Modes
Intel
DS
180
®
6300ESB I/O Controller Hub
Note: The Data Register (I/O Offset 00h) should be accessed using 16-bit or 32-bit I/O
Note: These registers are implemented in the IDE device. Therefore, accesses to these I/O
instructions. All other registers should be accessed using 8-bit I/O instructions.
registers cause corresponding accesses on the IDE interface.
IDE Legacy I/O Ports: Command Block Registers (CS1x# Chip Select)
In native mode, the Intel
offsets are used as in
BARs, rather than fixed I/O locations.
For accesses to the Alt Status register in the Control Block, the P-ATA host controller
must always force the upper address bit (PDA[2] or SDA[2]) to 1 in order to ensure
proper decode by the P-ATA device. Unlike the Legacy Mode fixed address location, the
Native Mode address for this register may contain a 0 in address bit 2 when it is
received by the P-ATA host controller.
IDE data port transaction latency consists of startup latency, cycle latency, and
shutdown latency.
Startup latency is incurred when a PCI master cycle targeting the IDE data port is
decoded and the DA[2:0] and CSxx# lines are not set up. Startup latency provides the
setup time for the DA[2:0] and CSxx# lines prior to assertion of the read and write
strobes (DIOR# and DIOW#).
Cycle latency consists of the I/O command strobe assertion length and recovery time.
Recovery time is provided so that transactions may occur back-to-back on the IDE
interface (without incurring startup and shutdown latency) without violating minimum
cycle periods for the IDE interface. The command strobe assertion width for the
enhanced timing mode is selected by the IDE_TIM Register and may be set to 2, 3, 4,
or 5 PCI clocks. The recovery time is selected by the IDE_TIM Register and may be set
to 1, 2, 3, or 4 PCI clocks.
When IORDY is asserted when the initial sample point is reached, no wait-states are
added to the command strobe assertion length. When IORDY is negated when the
initial sample point is reached, additional wait-states are added. Since the rising edge
of IORDY must be synchronized, at least two additional PCI clocks are added.
NOTE: For accesses to the Alt Status register in the Control Block, the Intel
I/O Offset
00h
01h
02h
03h
04h
05h
06h
07h
must always force the upper address bit (PDA[2] or SDA[2]) to 1 in order to ensure
proper native mode decode by the IDE device. Unlike the legacy mode fixed address
location, the native mode address for this register may contain a 0 in address bit 2 when
it is received by the Intel
Data
Error
Sector Count
Sector Number
Cylinder Low
Cylinder High
Drive
Status
Register Function (Read)
Table
®
6300ESB ICH will not decode the legacy ranges. The same
80, however, the base addresses are selected using the PCI
®
6300ESB ICH.
Features
Sector Count
Cylinder Low
Cylinder High
Command
Data
Sector Number
Head
Register Function (Write)
Order Number: 300641-004US
Intel
®
6300ESB ICH
®
6300ESB ICH—5
November 2007