NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 812

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 728. Power Management Timings
Intel
DS
812
NOTES:
t183a
t183b
t194a
t198a
t198b
t198d
t198e
1. These transitions are clocked off the internal RTC. 1 RTC clock is approximately 32 µs.
2. The Intel
3. These transitions are clocked off the 33 MHz PCICLK. 1 PCICLK is approximately 30ns.
4. The Intel
5. If the transition to S5 is due to Power Button Override, SLP_S3#, SLP_S4# and SLP_S5# are asserted
6. If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up together, the delay from
7. This value is programmable in multiples of 1024 PCI CLKs. Maximum is 8192 PCI CLKs (245.6 µs).).
Sym
t181
t182
t183
t184
t187
t188
t189
t190
t192
t193
t194
t195
t196
t197
t198
t220
cycle. The timing for this cycle getting to the Intel
memory controller.
designer to determine if the SLP_S3#, SLP_S4# and SLP_S5# signals are used to control the power planes.
together similar to timing t194 (PXPCIRST# active to SLP_S3# active).
RTCRST# and RSMRST# inactive to SUSCLK toggling may be as much as 2.5 s.
®
6300ESB I/O Controller Hub
VccSus active to SLP_S5#, SUS_STAT# and PXPCIRST#
active
RSMRST# inactive to SUSCLK running, SLP_S5# inactive
SLPS5# inactive to SLP_S4# inactive
SLPS4# inactive to SLP_S3# inactive
STPCLK# active to Stop Grant cycle
Stop Grant cycle to CPUSLP# active
S1 Wake Event to CPUSLP# inactive
CPUSLP# inactive to STPCLK# inactive
CPUSLP# active to SUS_STAT# active
SUS_STAT# active to PXPCIRST# active
PXPCIRST# active to SLP_S3# active
SLP_S3# active to SLP_S4# active
SLP_S4# active to SLP_S5# active
SLP_S3# active to PWROK inactive
PWROK inactive to Vcc supplies inactive
Wake Event to SLP_S5# inactive
Wake Event to SLP_S4# inactive(S4 Wake)
S3 Wake Event to SLP_S3# inactive(S3 Wake)
SLP_S5# inactive to SLP_S4# inactive
SLP_S4# inactive to SLP_S3# inactive
THRMTRIP# active to SLP_S3#, SLP_S4#, SLP_S5#
active
®
®
6300ESB ICH STPCLK# assertion will trigger the processor to send a stop grant acknowledge
6300ESB ICH has no maximum timing requirement for this transition. It is up to the system
Parameter
®
6300ESB ICH is dependant on the processor and the
3.87
Min
N/A
60
20
1
1
1
2
9
1
1
1
0
1
1
0
1
1
Max
110
N/A
245
50
50
63
25
21
10
10
2
2
4
2
2
2
2
2
2
2
PCI CLK
RTCCLK
RTCCLK
RTCCLK
RTCCLK
RTCCLK
RTCCLK
RTCCLK
RTCCLK
RTCCLK
RTCCLK
RTCCLK
RTCCLK
PCICLK
PCICLK
Units
ms
ms
µs
ns
ns
ns
Order Number: 300641-004US
Intel
Notes
®
1,
6
2
3
4
1
1
1
1
4
1
1
1
1
1
6300ESB ICH—22
5
November 2007
Figure 62
Figure 62
Figure 62
Figure 62
Figure 62
Figure 64
Figure 63
Figure 63
Figure 64
Figure 63
Figure 63
Figure 64
Figure 64
Figure 64
Figure 64
Figure 64
Figure 64
Figure 64
Figure 64
Fig