NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 314

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.1.4
Table 184. Offset 06 - 07h: PCISTA—PCI Device Status (LPC I/F—D31:F0)
Intel
DS
314
10:9
Bits
Default Value:
4:0
15
14
13
12
11
8
7
6
5
®
6300ESB I/O Controller Hub
Lockable:
Device:
FB2B: Fast Back to Back
DPED: Data Parity Error
Offset:
RMA: Received Master
SSE: Signaled System
66MHZ_CAP: 66 MHz
DPE: Detected Parity
RTA: Received Target
STA: Signaled Target
DEV_STS: DEVSEL#
UDF: User Definable
Timing Status
Offset 06 - 07h: PCISTA—PCI Device Status
(LPC I/F—D31:F0)
Reserved
Detected
Features
Capable
31
06-07h
0280h
No
Name
Abort
Abort
Abort
Error
Error
0 = This bit is cleared by software writing a 1 to the bit
1 = PERR# signal goes active. Set even when the PER bit is 0.
0 = This bit is cleared by software writing a 1 to the bit
1 = Set by the Intel
0 = This bit is cleared by software writing a 1 to the bit
1 = The Intel
0 = This bit is cleared by software writing a 1 to the bit
1 = The Intel
0 = This bit is cleared by software writing a 1 to the bit
1 = The Intel
01 = Medium Timing.
0 = This bit is cleared by software writing a 1 to the bit
1 = Set when all three of the following conditions are true:
Always 1. Indicates the Intel
accept fast back-to-back transactions.
Hardwired to 0
Hardwired to 0
Reserved.
position.
position.
and the Intel
function 0. The ERR_STS register may be read to
determine the cause of the SERR#. The SERR# may be
routed to cause SMI#, NMI, or interrupt.
position.
PCI due to LPC I/F master or DMA cycles.
position.
LPC I/F master or DMA cycles to PCI.
position.
condition on PCI cycles claimed by the Intel
ICH for Intel
going to LPC I/F.
position.
- The Intel
- The Intel
observed PERR# (for writes), and
- The PER bit is set.
®
®
®
®
®
6300ESB ICH generated a master abort on
6300ESB ICH received a target abort during
6300ESB ICH generated a target abort
®
6300ESB ICH asserted PERR# (for reads) or
®
6300ESB ICH is the initiator of the cycle,
6300ESB ICH internal registers or for
6300ESB ICH generates an SERR# on
®
6300ESB ICH n the SERR_EN bit is set
Power Well:
Description
Attribute:
Function:
®
Size:
6300ESB ICH as a target may
0
Read/Write Clear
16-bit
Core
®
6300ESB
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/WC
R/W
R/W
R/W
R/W
R/W
RO
RO
RO