NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 676

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18.6.1.28Offset 54: PX_BSTS - PCI-X Bridge Status
Intel
DS
676
31:2
Bits
Bits
02
01
00
21
20
19
2
®
Table 610. Offset 52: PX_SSTS—PCI-X Secondary Status (Sheet 2 of 2)
Table 611. Offset 54: PX_BSTS - PCI-X Bridge Status
6300ESB I/O Controller Hub
Note: Identifies PCI-X capabilities and current operating mode of the bridge.
Unexpected
Completion
Completion
Completion
Device
Device
Discarded
Offset
Offset
Reserved
133 MHz
Capable
Request
Delayed
Overrun
(C133)
Name
Device
Name
(SCO)
(SCD)
64-bit
(D64)
(SRD)
(USC)
Split
Split
Split
Split
28
52
28
54
This bit is set when the Intel
completion moving toward the secondary bus because the
requester would not accept it. This bit is cleared by software
writing a ‘1’.
This bit indicates that the Intel
interface is capable of 133 MHz operation in PCI-X mode.
0 = Not capable
1 = Capable
Indicates the width of the secondary bus as 64-bits.
Reserved.
The Intel
The Intel
not request more data on the Hub Interface than it may
receive.
This does not apply to Hub Interface, which is the primary
interface.
®
®
6300ESB ICH does not set this bit because it does
6300ESB ICH does not support this bit.
Description
Description
®
6300ESB ICH discards a split
®
6300ESB ICH’s secondary
Attribute:
Attribute:
Function
Function
Size:
Size:
0
Read-Only
16-bit
0
Read-Only
32-bit
Order Number: 300641-004US
Reset
Value
Reset
Value
Intel
0
0
1
0
0
0
0
®
6300ESB ICH—18
November 2007
Access
Access
R/WC
RO
RO
RO
RO
RO
RO