NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 431

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.10.7
Table 319. Offset GPIOBASE + 30h:GPIO_USE_SEL2—GPIO Use Select 2 Register
November 2007
Order Number: 300641-004US
Implementation Note: Bits 26:31 may be in CORE Well.
31:2
25:2
23:1
11:8
Bits
Default Value:
7:0
6
4
2
Lockable:
®
Device:
Offset:
6300ESB ICH
Offset GPIOBASE + 30h:GPIO_USE_SEL2—GPIO
Use Select 2 Register
31
GPIOBASE +30h
03000000h
No
Name
Always 0. No corresponding GPIO.
Always 1. These pins are unmuxed.
Always 0. No corresponding GPIO.
GPIO_USE_SEL[43:40]: Enables GPIO[n] (where n is the
bit number) to be used as a GPIO, rather than for the native
function. Since these pins may be used as outputs for
controlling power planes, switching the pin from functional to
GPO mode must be glitch-free.
1 = Signal used as GPIO (or unmuxed).
0 = Signal used as native function.
After a full reset(RSMRST#) all multiplexed signals in the
resume and core wells are configured as their native function
rather than as a GPIO. After just a PXPCIRST#, the GPIO in
the core well are configured as GPIO.
GPIO_USE_SEL[39:32]: Enables GPIO[n] (where n is the
bit number) to be used as a GPIO, rather than for the native
function. Since these pins may be used as outputs for
controlling power planes, switching the pin from functional to
GPO mode must be glitch-free.
1 = Signal used as GPIO (or unmuxed).
0 = Signal used as native function.
After a full reset(RSMRST#) all multiplexed signals in the
resume and core wells are configured as their native function
rather than as a GPIO. After just a PXPCIRST#, the GPIO in
the core well are configured as GPIO.
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
32-bit
Core for 55:32 = bits 23:0
Resume for 63:56 = bits 31:24
Intel
®
6300ESB I/O Controller Hub
Access
431
DS