NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 699

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18—Intel
18.10.2 Prefetch Algorithm
18.10.2.1Parameters
18.10.2.2Algorithm (Single Device Only)
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Since outbound cycles are not prefetched, there is no algorithm. The algorithm for
inbound cycles is below. Note that the algorithm changes depending upon whether only
one device is requesting or multiple devices are requesting.
Parameters based upon the Prefetch Parameter Registers at offset F8h – FFh
Ri
Ti
Rs
Ts
D
Other Algorithm Parameters
Sb
N
B
1. Establish DT, launch request of size Ri. The actual amount fetched is such that the
2. Wait until at least some data has returned and master has reconnected. In PCI
3. When N < Ti, launch a request of size Rs (truncated by Sb, when necessary). Start
4. Check for size B vs. Ts
transfer ends on a naturally aligned 128-byte line. When the initial address is less
than 64-bytes into the 128-byte line, the Ri value is rounded down (i.e., eight 64-
byte lines become seven 64-byte lines + remainder). When the initial address is
more than 64-bytes into the 128-byte line, the Ri value is rounded up (i.e., eight
64-byte lines become nine 64-byte lines + remainder).
Example 1: Address starts at 32 bytes into a 128-byte line, and the fetch
length is 4*64 byte lines (256 bytes). The amount fetched is 256 - 32 =
224 bytes (56 dWords).
Example 2: Address starts at 96 bytes into a 128-byte line, and the fetch
length is 4*64-byte lines (256 bytes). The amount fetched is 256 + (128 -
96) = 288 bytes (72 dWords).
mode, this is when the first qWord becomes available. In PCI-X, when not running
in 133 MHz mode, or running in 133 MHz mode but the request size is less than or
equal to 256 bytes, this is when the first ADB becomes available.
Timer when there are not more active delayed transactions. When there are other
active delayed transactions, go to step 5.
When B < Ts, wait for timer to expire before launch of size Rs. Restart
timer. Go to Step 4.
When B > Ts before timer expires, reset timer. Go to Step 5.
Initial request size (bits[03:00])
Initial threshold (bits[07:04])
Subsequent request (bits [11:08])
Subsequent threshold (bits[15:12])
Delay to wait between next Ts (calculated). The value is
“Rs:111” clocks.
Buffer size (either 1K or 2K, depending upon the delayed
transaction bit (offset 40h, bit 2))
Data in buffer + data in flight (requested to SiBUS but not
returned)
Data in buffer
Intel
®
6300ESB I/O Controller Hub
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