NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 161

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
Table 73.
5.11.9.3 PME# - PCI Power Management Event
5.11.9.4 SYS_RESET# Signal
5.11.9.5 THRMTRIP# Signal
November 2007
Order Number: 300641-004US
®
6300ESB ICH
Transitions Due to RI# Signal
The PME# signal comes from a PCI device to request that the system be restarted. The
PME# signal may generate an SMI#, SCI, or optionally a Wake event. The event occurs
when the PME# signal goes from high to low. No event is caused when it goes from low
to high. The Intel
between both the PCI and the PCI-X interfaces.
In the EHCI controller, there is an internal PME_B0 bit. This is separate from the
external PME# signal and may cause the same effect.
SYS_RESET# is a new pin on the Intel
glue logic on the board. Before the addition of this pin, a system reset was activated by
external glue forcing the PWROK signal low after the reset button was pressed. This pin
eliminates the need for that glue. As such, a SYS_RESET# event should look internally
to our chip and externally to the system as when PWROK had gone low.
When the SYS_RESET# pin is detected as active after the 16 ms debounce logic, the
Intel
for the SMBus to go idle. When the SMBus is idle when the pin is detected active, the
reset will occur immediately, otherwise the counter will start. When at any point during
the count the SMBus goes idle the reset will occur. When, however, the counter expires
and the SMBus is still active, a reset will be forced upon the system even though
activity is still occurring.
Once a reset of this type has occurred, it cannot occur again until SYS_RESET# has
been detected inactive after the debounce logic, and the system is back to a full S0
state as indicated by all of the PWROK inputs being active.
When THRMTRIP# goes active, the processor is indicating an overheat condition, and
the Intel
processor has overheated, it will not respond to the Intel
with a stop grant special cycle. Therefore, the Intel
Immediately upon seeing THRMTRIP# low, the Intel
transition to the S5 state, drive SLP_S3#, SLP_S4#, SLP_S5# low, and set the CTS bit.
The transition will look like a power button override.
It is extremely important that when a THRMTRIP# event occurs, the Intel
ICH power down immediately without following the normal S0 -> S5 path. This path
may be taken in parallel, but the Intel
down state. It will do this by driving SLP_S3#, SLP_S4#, and SLP_S5# immediately
after sampling THRMTRIP# active.
Present State
NOTE: Filtering/Debounce on RI# will not be done in the Intel
®
S1-S5
S0
6300ESB ICH will attempt to perform a “graceful” reset, by waiting up to 25 ms
or external.
®
6300ESB ICH will immediately transition to an S5 state. However, since the
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RI# Active
RI# Active
Event
6300ESB ICH supports only one PME# signal which is shared
RI_EN
X
0
1
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6300ESB ICH must immediately enter a power
6300ESB ICH that is used to eliminate extra
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®
6300ESB ICH will not wait for one.
6300ESB ICH will initiate a
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®
6300ESB ICH. Can be in modem
6300ESB ICH’s STPCLK# pin
Wake Event
Intel
Ignored
Ignored
Event
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6300ESB I/O Controller Hub
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6300ESB
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