NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 635

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NHE6300ESB S L7XJ

Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet

Specifications of NHE6300ESB S L7XJ

Lead Free Status / RoHS Status
Compliant
17—Intel
17.1.6
Table 563. Offset 0C - 0Fh: HEADTYP—Header Type Register (APIC1—D29:F5)
17.1.7
Table 564. Offset 2C - 2Fh: SS—APIC1 Subsystem Identifiers (APIC1—D29:F5)
November 2007
Order Number: 300641-004US
31:2
23:1
15:0
31:1
15:0
Bits
Bits
Default Value:
Default Value:
4
6
6
Lockable:
Note: This register is initialized to logic ‘0’ by the assertion of PXPCIRST#. This register may
Device:
Device:
®
Offset:
Offset:
SSID: Subsystem ID
6300ESB ICH
SSVID: Subsystem
Header Type
Vendor ID
(APIC1—D29:F5)
Offset 2C - 2Fh: SS—APIC1 Subsystem Identifiers
(APIC1—D29:F5)
be written only once after PXPCIRST# deassertion.
Offset 0C - 0Fh: HEADTYP—Header Type Register
Reserved
Reserved
29
0C - 0Fh
00000000h
Name
29
2C - 2Fh
0000000h
No
Name
Reserved.
This indicates that it is a type ‘00’ header (normal PCI device)
and that it is a single function device.
Reserved.
Write once register for subsystem ID.
Write once register for holding the subsystem vendor ID.
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
5
Read-Only
32-bit
5
Read/Write Once
32-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
Access
RWO
RWO
RO
635
DS

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