NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 721

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

19—Intel
Table 647. Modem Control Register (MCR) (Sheet 2 of 2)
19.5.1.3.9 Modem Status Register (MSR)
Table 648. Modem Status Register (MSR) (Sheet 1 of 2)
November 2007
Order Number: 300641-004US
®
6300ESB ICH
This 8 bit register provides the current state of the control lines from the modem or
data set (or a peripheral device emulating a modem) to the processor. In addition to
this current state information, four bits of the Modem Status register provide change
information. These bits, 3:0, are set to a logic ’1’ when a control input from the Modem
changes state. They are reset to a logic ’0’ when the processor writes ’1’s to the bits of
the Modem Status register.
When bits 0, 1, 2, or 3 are set to logic 1, a Modem Status interrupt is generated if bit 3
of the Interrupt Enable Register is set.
Modem Status Register
MSR
read only
Bit Number
0
7
6
5
4
3
Bit Mnemonic
DDCD
DCD
DSR
DTR
CTS
RI
Data Terminal Ready: This bit controls the Data Terminal
Ready output. When bit 0 is set to a logic ‘1’, the DTR# output is
force to a logic ‘0’. When bit 0 is reset to a logic ‘0’, the DTR#
output pin is forced to a logic ‘1’.
0 = DTR# pin is 1
1 = DTR# pin is 0
Address:
Reset State:
Access:
Data Carrier Detect: This bit is the complement of the Data
Carrier Detect (DCD#) input. This bit is equivalent to bit OUT2
of the Modem Control register if LOOP in the MCR is set to 1.
0 = DCD# pin is 1
1 = DCD# pin is 0
Ring Indicator: This bit is the complement of the ring
Indicator (RI#) input. This bit is equivalent to bit OUT1 of the
Modem Control register if LOOP in the MCR is set to 1.
0 = RI# pin is 1
1 = RI# pin is 0
Data Set Ready: This bit is the complement of the Data Set
Ready (DSR#) input. This bit is equivalent to bit DTR of the
Modem Control register if LOOP in the MCR is set to 1.
0 = DSR# pin is 1
1 = DSR# pin is 0
Clear to Send: This bit is the complement of the Clear to
Send (CTS#) input. This bit is equivalent to bit RTS of the
Modem Control register if LOOP in the MCR is set to 1.
0 = CTS# pin is 1
1 = CTS# pin is 0
Delta Data Carrier Detect:
0 = No change in DCD# pin since last read of MSR.
1 = DCD# pin has changed state.
• The DTR# output of the UART may be applied to an EIA
inverting line driver (such as the DS1488) to obtain the
proper polarity input at the succeeding modem or data set.
Function
Base + 06H
00H
8-bit
Intel
®
6300ESB I/O Controller Hub
721
DS