NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 756

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

20.1.27 Offset 74 - 75h: PMCS—PCI Power Management
Intel
DS
756
14:9
Bits
Bits
Default Value:
Default Value:
8:6
2:0
7:2
1:0
15
5
4
3
8
®
Table 685. Offset 72 - 73h: PC—PCI Power Management Capabilities (SATA–
Table 686. Offset 74 - 75h: PMCS—PCI Power Management Control and Status
6300ESB I/O Controller Hub
Device:
Device:
Offset:
Offset:
Device Specific Initial-
PME Enable (PMEE).
PME Status (PMES)
PME Clock (PMEC)
Power State (PS)
Aux_Current
ization (DSI)
Version (VS)
D31:F2)
Control and Status (SATA–D31:F2)
(SATA–D31:F2)
Reserved
Reserved
Reserved
31
72-73h
0002
Name
31
74-75h
0000h
Name
Reports 375mA maximum Suspend well current required
when in the D3cold state.
Indicates that no device-specific initialization is required.
Reserved.
Indicates that PCI clock is not required to generate PME#.
Indicates support for Revision 1.1 of the PCI Power
Management Specification.
Reserved as ‘0’.
Reserved.
Reserved as ‘0’.
Reserved.
Power State (PS). These bits are used both to determine
the current power state of the SATA Controller and to set a
new power state.
00: D0 state
01: D1 state
10: D2 state
11: D3hot state
When in the D3hot state, the controller’s configuration space
is available, but the I/O and memory spaces are not.
Additionally, interrupts are blocked.
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
2
Read-Only
16-bit
2
Read-Only, Read/Write
16-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—20
November 2007
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