NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 266

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Intel
DS
266
®
6300ESB I/O Controller Hub
A new audio input frame begins with a low to high transition of AC_SYNC. AC_SYNC is
synchronous to the rising edge of BIT_CLK. On the immediately following falling edge
of BIT_CLK, the receiver samples the assertion of AC_SYNC. This falling edge marks
the time when both sides of AC-link are aware of the start of a new audio frame. On the
next rising edge of BIT_CLK, the codec transitions AC_SDIN into the first bit position of
slot 0 (codec ready bit). Each new bit position is presented to AC-link on a rising edge
of BIT_CLK, and subsequently sampled by the Intel
falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent
sample points for both incoming and outgoing data streams are time aligned.
SDIN data stream must follow the AC’97 specification and be MSB justified with all non-
valid bit positions (for assigned and/or unassigned time slots) stuffed with zeros.
AC_SDIN data is sampled by the Intel
®
6300ESB ICH on the falling edge of BIT_CLK.
®
6300ESB ICH on the following
Order Number: 300641-004US
Intel
®
6300ESB ICH—5
November 2007