NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 630

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

16.5.3
16.5.4
Intel
DS
630
®
6300ESB I/O Controller Hub
Note: Any subsequent writes require that this sequence be performed again.
The following is an example of how to prevent a timeout:
Reload Sequence
To keep the timer from causing an interrupt or driving WDT TOUT#, the timer must be
updated periodically. Other timers refer to updating the timer as “kicking” the timer.
The frequency of updates required is dependent on the value of the Preload values. To
update the timer, the Register Unlocking Sequence must be performed followed by
writing a ‘1’ to bit 8 at offset BAR+ 0Ch within the watchdog timer memory mapped
space. This sequence of events is referred to as the “Reload Sequence”.
Low Power State
The Watchdog Timer does not operate when PCICLK is stopped.
1. Write 80 to offset BAR + 0Ch.
2. Write 86 to offset BAR + 0Ch.
3. Write a ‘1’ to RELOAD [8] (WDT_RELOAD) of the Reload Register.
Order Number: 300641-004US
Intel
®
6300ESB ICH—16
November 2007