NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 220

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 106. USB Legacy Keyboard State Transitions
Intel
DS
220
GateState1
GateState1
GateState1
GateState1
GateState1
GateState2
GateState2
GateState2
Current
®
State
IDLE
IDLE
IDLE
IDLE
IDLE
6300ESB I/O Controller Hub
64h / Write
64h / Write
60h / Write
60h / Write
64h / Write
64h / Write
64h / Write
64h / Read
60h / Read
60h / Read
64h / Read
64h / Read
64 / Write
Action
Don't Care
Not D1h
Not D1h
Not FFh
Value
Data
D1h
D1h
XXh
N/A
N/A
N/A
N/A
FFh
N/A
GateState
GateState
GateState
GateState
GateState
State
Next
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
1
2
1
1
2
Standard D1 command. Cycle passed through to 8042.
SMI# doesn't go active. PSTATE (offset C0, bit 6) goes
to 1.
Bit 3 in Config Register determines if cycle passed
through to 8042 and if SMI# generated.
Bit 2 in Config Register determines if cycle passed
through to 8042 and if SMI# generated.
Bit 1 in Config Register determines if cycle passed
through to 8042 and if SMI# generated.
Bit 0 in Config Register determines if cycle passed
through to 8042 and if SMI# generated.
Cycle passed through to 8042, even if trap enabled in
Bit 1 in Config Register. No SMI# generated. PSTATE
remains 1. When data value is not DFh or DDh then
the 8042 may chose to ignore it.
Cycle passed through to 8042, even if trap enabled
through Bit 3 in Config Register. No SMI# generated.
PSTATE remains 1. Stay in GateState1 because this is
part of the double-trigger sequence.
Bit 3 in Config space determines if cycle passed
through to 8042 and if SMI# generated. PSTATE goes
to 0. When Bit 7 in Config Register is set, then SMI#
should be generated.
This is an invalid sequence. Bit 0 in Config Register
determines if cycle passed through to 8042 and if
SMI# generated. PSTATE goes to 0. When Bit 7 in
Config Register is set, then SMI# should be generated.
Just stay in same state. Generate an SMI# when
enabled in Bit 2 of Config Register. PSTATE remains 1.
Standard end of sequence. Cycle passed through to
8042. PSTATE goes to 0. Bit 7 in Config Space
determines if SMI# should be generated.
Improper end of sequence. Bit 3 in Config Register
determines if cycle passed through to 8042 and if
SMI# generated. PSTATE goes to 0. When Bit 7 in
Config Register is set, then SMI# should be generated.
Just stay in same state. Generate an SMI# when
enabled in Bit 2 of Config Register. PSTATE remains 1.
Comment
Order Number: 300641-004US
Intel
®
6300ESB ICH—5
November 2007