NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 644

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

17.2.8
17.2.9
Intel
DS
644
31:1
63:5
55:4
47:1
Bits
Bits
Default Value:
Default Value:
17
0
6
8
8
®
Table 580. Offset 03h: BOOT_CONFIG—Boot Configuration Register
Table 581. Redirection Table (Sheet 1 of 3)
6300ESB I/O Controller Hub
Note: This register is used to control the interrupt delivery mechanism for the APIC.
Note: The APIC will respond to an edge-triggered interrupt as long as the interrupt is held
Device:
Device:
Extended Destination ID
Offset:
Offset:
DT: Delivery Type
Disable Flushing
Destination
Offset 03h: BOOT_CONFIG—Boot Configuration
Register
Redirection Table
The Redirection Table has a dedicated entry for each interrupt input pin. The
information in the Redirection Table is used to translate the interrupt manifestation on
the corresponding interrupt pin into an APIC message.
until after the acknowledge cycle has begun. Once the interrupt is detected, a delivery
status bit internally to the I/O APIC is set. The state machine will step ahead and wait
for an acknowledgment from the APIC bus unit that the interrupt message was sent
over the APIC bus. Only then will the I/O APIC be able to recognize a new edge on that
interrupt pin. That new edge will only result in a new invocation of the handler if its
acceptance by the destination APIC causes the Interrupt Request Register bit to go
from ‘0’ to ‘1’. (i.e., if the interrupt was not already pending at the destination.)
Reserved
Reserved
(DFLSH)
(EDID)
29
03h
00000001h
Name
29
10h-11h (vector 0)
through
3E-3Fh (vector 23)
Bit 16-1, Bits[15:12]=0.
All other bits undefined
Name
Reserved.
Hardwire to 1. Interrupt delivery mechanism is always a
Processor System Bus message.
When bit 11 of this entry is 0 [Physical], bits [59:56] specify
an APIC ID. In this case, bits 63:59 should be programmed
by software to 0. When bit 11 of this entry is ’1’ [Logical], bits
[63:56] specify the logical destination address of a set of
processors.
These bits are only sent to a local APIC when in Processor
System Bus mode. They become bits [11:4] of the address.
Reserved. Software should program these bits to 0.
This bit is maintained for any potential software compatibility,
but the Intel
regardless of the setting of this bit.
®
6300ESB ICH performs no flushing action,
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
5
Read-Only
32-bit
5
Read/Write
64 bits each, accessed as two 32 bit
quantities
Order Number: 300641-004US
Intel
®
6300ESB ICH—17
November 2007
Access
Access
R/W
RO