NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 306

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

7.1.27
Table 173. Offset 50 - 51h: CNF—Intel® 6300ESB ICH Configuration Register
Intel
DS
306
15:1
12:1
Bits
Default Value:
5:3
1:0
13
4
0
9
8
7
6
2
®
6300ESB I/O Controller Hub
Device:
HI-PCI Write Combining
Offset:
Hole Enable (15 MB-16
Delayed Transaction
Prefetch Flush Enable
Discard Timer
HP_PCI_EN
Offset 50 - 51h: CNF—Intel
Configuration Register (HUB-PCI—D30:F0)
(HUB-PCI—D30:F0)
NOTE: Refer to the latest revision of the Intel
Reserved
Reserved
Reserved
Reserved
Reserved
Enable
30
50-51h
1400h
Name
MB)
recommended configuration of this register.
Reserved.
Prefetch Flush Enable.
0 = Prefetch Flush Disable
1 = Causes CPU to PCI logic to only deliver “Demand” data
for a delayed transaction if a processor-to-PCI write has
occurred since the delayed transaction was initiated.
(Default)
NOTE: This bit must be set by system BIOS.
Reserved.
High Priority PCI Enable
0 = All PCI REQ#/GNT pairs have the same arbitration
1 = Enables a mode where the REQ[0]#/GNT[0]# signal pair
0 = Disable
1 = Enables the 15 Mbyte to 16 Mbyte hole in the DRAM.
Reserved.
HI-PCI Write Combining Enable
1 = Disables Hub Interface to PCI Write combining
Reserved.
Delayed Transaction Discard Timer
When set to 1 this bit shortens all delayed transaction discard
timers to 128 PCI clocks.
Reserved.
priority.
has a higher arbitration priority.
Description
Attribute:
Function:
®
6300ESB ICH BIOS Specification for the
Size:
®
6300ESB ICH
0
Read/Write
16-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—7
November 2007
Access
R/W
R/W
R/W
R/W
R/W