NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 263

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.20.2.1 AC-link Output Frame (SDOUT)
5.20.2.2 Output Slot 0: Tag Phase
November 2007
Order Number: 300641-004US
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6300ESB ICH
not distinguish between codecs on its AC_SDIN[2:0] pins, however the registers do
distinguish between AC_SDIN[0], AC_SDIN[1], and AC_SDIN[2] for wake events, etc.
When using a Modem Codec it is recommended to connect it to AC_SDIN[1].
See your Platform Design Guide for a matrix of valid codec configurations.
The Intel
specification.
A new output frame begins with a low to high transition of AC_SYNC. AC_SYNC is
synchronous to the rising edge of BIT_CLK. On the immediately following falling edge
of BIT_CLK, the codec samples the assertion of AC_SYNC. This falling edge marks the
time when both sides of AC-link are aware of the start of a new frame. On the next
rising edge of BIT_CLK, the Intel
position of slot 0, or the valid frame bit. Each new bit position is presented to the AC-
link on a rising edge of BIT_CLK, and subsequently sampled by the codec on the
following falling edge of BIT_CLK. This sequence ensures that data transitions and
subsequent sample points for both incoming and outgoing data streams are time
aligned.
The output frame data phase corresponds to the multiplexed bundles of all digital
output data targeting codec DAC inputs and control registers. Each output frame
supports up to twelve outgoing data time slots. The Intel
or 20 bits and stuffs remaining bits with zeros.
The output data stream is sent with the most significant bit first, and all invalid slots
are stuffed with zeros. When mono audio sample streams are output from the Intel
6300ESB ICH, software must ensure both left and right sample stream time slots are
filled with the same data.
Slot 0 is considered the tag phase. The tag phase is a special 16 bit time slot wherein
each bit conveys a valid tag for its corresponding time slot within the current frame. A
one in a given bit position of slot 0 indicates that the corresponding time slot within the
current frame has been assigned to a data stream and contains valid data. When a slot
is tagged invalid with a zero in the corresponding bit position of slot 0, the Intel
6300ESB ICH stuffs the corresponding slot with zeros during that slot’s active time.
Within slot 0, the first bit is a valid frame bit (slot 0, bit 15) which flags the validity of
the entire frame. When the valid frame bit is set to one, this indicates that the current
frame contains at least one slot with valid data. When there is no transaction in
progress, the Intel
write to slot 12, that slot will always stay valid, and therefore the frame valid bit will
remain set.
The next 12 bit positions of slot 0 (bits [14:3]) indicate which of the corresponding
twelve time slots contain valid data. Bits [1:0] of slot 0 are used as codec ID bits to
distinguish between separate codecs on the link.
Using the valid bits in the tag phase allows data streams of differing sample rates to be
transmitted across the link at its fixed 48 KHz frame rate. The codec may control the
output sample rate of the Intel
the AC’97 specification.
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6300ESB ICH does not support optional test modes as outlined in the AC’97
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6300ESB ICH will deassert the frame valid bit. Note that after a
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6300ESB ICH using the SLOTREQ bits as described in
6300ESB ICH transitions SDOUT into the first bit
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6300ESB ICH generates 16
Intel
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6300ESB I/O Controller Hub
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