NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 706

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

19.3
19.3.1
Table 631. Address Map
19.4
19.4.1
Table 632. Supported LPC Cycle Types
19.4.1.1 I/O Read and Write Cycles
Intel
DS
706
®
6300ESB I/O Controller Hub
Functional Description
Host Processor Interface (LPC)
The host processor communicates with the SIU through the LPC bus. Access is through
a series of read/write registers and accomplished through I/O cycles or DMA transfers.
All registers are 8 bits wide. The SIU registers include global configuration space and
device specific regions accessed by setting the Logical Device Number in the SIU
Configuration Register 07H (SCR7). See
See
base address.
LPC Interface
The LPC interface is used to control all the logical blocks on the SIU. LPC bus signals
use PCI 33 MHz electrical signal characteristics. Refer to the Low Pin Count (LPC)
Interface Specification, Rev 1.0.
LPC Cycles
The following cycle types are supported by the LPC protocol.
The SIU ignores cycles that it does not support.
The SIU is the target for I/O cycles. I/O cycles are initiated by the host for register or
FIFO accesses and will generally have minimal Sync times.
Data transfers are assumed to be exactly 1-byte. If the processor requested a 16- or
32-bit transfer, the host must break it up into 8-bit transfers.
See the Low Pin Count (LPC) Interface Specification for the sequence of cycles for the
I/O Read and Write cycles.
Cycle Type
Section 19.8, “Configuration”
I/O Write
I/O Read
Base+(0-7)
Base+(0-7)
060h/064h
Address
04Eh
04Fh
Transfer Size
1 Byte
1 Byte
for configuration register descriptions and setting the
Port 60/64 Emulation
Configuration Index
Configuration Data
Table
Serial Port Com 1
Serial Port Com 2
Block Name
631.
Order Number: 300641-004US
Intel
Logical Device
®
6300ESB ICH—19
November 2007
04H
05H
07h