NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 678

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18.6.1.29Offset 58: PX_USTC - PCI-X Upstream Split Transaction
18.6.1.30Offset 5C: PX_DSTC - PCI-X Downstream Split Transaction
Intel
DS
678
31:1
15:0
Bits
6
0
®
Table 612. Offset 58: PX_USTC - PCI-X Upstream Split Transaction Control
6300ESB I/O Controller Hub
Note: This register identifies controls behavior of the PCI-X Upstream Split Control buffers for
Note: The Intel
Note: This register controls behavior of the PCI-X Downstream Split Control buffers for
Note: The Intel
Transaction
Transaction
Limit (STL)
Device
Offset
Capacity
Name
(STC)
Split
Split
Control
forwarding Split Transactions from the secondary bus to the Hub Interface.
required by end users.
Control
forwarding Split Transactions from the Hub Interface to the secondary bus.
required by end users.
28
58
R/W field available for use by diagnostic software.
NOTE: Not used by the Intel
Infinite capacity due to launch algorithm keeping buffers from
overrunning. The Intel
algorithms keep buffers from being overallocated.
®
®
6300ESB ICH maintains these registers internally; programming is not
6300ESB ICH maintains these registers internally, programming not
“commitment” level. The Intel
launch algorithms keep buffers from being
overallocated.
®
Description
6300ESB ICH internal launch
®
6300ESB ICH for modifying its
®
Attribute:
6300ESB ICH internal
Function
Size:
0
Read/Write
32-bit
Order Number: 300641-004US
Reset
Value
0000h
FFFFh
Intel
®
6300ESB ICH—18
November 2007
Access
R/W
RO