NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 176

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5.13
5.13.1
Table 79.
Intel
DS
176
NOTES:
1. GPIO[0:7], GPIO[16:21, 23], and GPIO[32:43] are in the core well.
2. GPIO[8:13] and GPIO[24:28] are in the suspend well.
3. Core-well GPIO are 5V tolerant, except for GPIO[7:6] and [32:43].
4. Resume-well GPIO are not 5V tolerant.
5. GPIO[56:57] pads are in the suspend well, the register bits are in the RTC well.
GPI[2:5]
GPI[11]
GPI[12]
GPI[13]
GPI[0]
GPI[1]
GPI[6]
GPI[7]
GPI[8]
GPIO
®
6300ESB I/O Controller Hub
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Only
Only
Only
Only
Only
Only
Only
Only
Only
General Purpose I/O
GPIO Mapping
GPIO Implementation (Sheet 1 of 2)
PIRQ[E:H]#
SMBALERT#
PXREQ[2]#
PXREQ[3]#
Alternate
Function
Unmuxed
Unmuxed
Unmuxed
Unmuxed
Unmuxed
Power
Resum
Resum
Resum
Resum
Well
Core
Core
Core
Core
Core
e
e
e
e
Tolera
5.0 V
5.0 V
5.0 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
nt
GPIO_USE_SEL bit 0 enables REQ/GNT[A]# pair.
Input active status read from GPE0_STS register bit
16.
Input active high/low set through GPI_INV register bit
0.
NOTE: GPEO_STS register,
GPIO_USE_SEL bit 1 enables REQ/GNT[B]# pair.
Input active status read from GPE0_STS register bit
17
Input active high/low set through GPI_INV register bit
1.
GPIO_USE_SEL bits [2:5] enable PIRQ[E:H]#.
Input active status read from GPE0_STS reg. bits
[18:21].
Input active high/low set through GPI_INV reg. bit
[2:5].
Input active status read from GPE0_STS register bit
22.
Input active high/low set through GPI_INV register bit
6.
Input active status read from GPE0_STS register bit
23.
Input active high/low set through GPI_INV register bit
7
Input active status read from GPE0_STS register bit
24.
Input active high/low set through GPI_INV register bit
8.
GPIO_USE_SEL bit 11 enables SMBALERT#
Input active status read from GPE0_STS register bit
27.
Input active high/low set through GPI_INV register bit
11.
Input active status read from GPE0_STS register bit
28.
Input active high/low set through GPI_INV register bit
12.
Input active status read from GPE0_STS register bit
29.
Input active high/low set through GPI_INV register bit
13.
register,
Section 8.10.6
Notes
Section 8.8.3.7
Order Number: 300641-004US
Intel
®
6300ESB ICH—5
November 2007
GPI_INV