NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 684

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18.7
18.7.1
18.7.2
Table 619. Intel
Intel
DS
684
®
6300ESB I/O Controller Hub
PCI Mode in the PCI-X Interface
This section discusses the specifics of the PCI interface associated with the PCI-X
interface while operating in PCI mode. The PCI section of this document describes the
“legacy” PCI which is not visible external to the chip. PCI-X is not mentioned in this
section. To see specifics on how the PCI-X interface operates, refer to
“PCI-X
Summary of Changes
For the most part, the PCI interface of the Intel
the PCI interface for the P64H2.
Transaction Types
As a PCI master, the Intel
target, the Intel
address space. The Intel
only for bursting memory transfers (indicated when the low two address bits are equal
to ’0’). When either of these address bits is nonzero, the Intel
disconnects the transaction after the first data transfer.
† The Intel
0000
0001
0010
0011
0100
0101
0110
0111
•
•
•
•
reserved command codes as a target.
Full 64 bit addressing inbound
Inbound packet size based upon cache line size of the platform.
I/O space may be programmed to 1K granularity through the EN1K bit of the CNF
register.
When inbound reads are retried, they are moved to the side so posted writes and
completion packets may pass. I/O reads and writes on PCI are no longer be
forwarded to the Hub Interface.
Type of Transaction
®
Interface”.
6300ESB I/O Controller Hub PCI Transactions
®
Memory write
Memory read
acknowledge
Special cycle
6300ESB ICH never initiates a PCI transaction with a reserved command code and ignores
Reserved
Reserved
Interrupt
I/O write
I/O read
®
6300ESB ICH may accept dual address cycles up to the full 64-bit
†
†
®
®
6300ESB ICH supports the linear increment address mode
6300ESB ICH has access to the 32-bit address space. As a
Maste
6300ESB ICH
Yes
Yes
Yes
Yes
Yes
No
No
No
r
Intel
as
Targe
®
Yes
Yes
No
No
No
No
No
No
t
1000
1001
1010
1011
1100
1101
1110
1111
®
Type of Transaction
6300ESB ICH is exactly the same as
Configuration Write
Dual Address Cycle
Configuration Read
Memory Read Line
Memory Write and
Memory Read
Reserved
Reserved
Invalidate
Multiple
®
Order Number: 300641-004US
6300ESB ICH
†
†
Intel
Section 18.8,
®
6300ESB ICH—18
Maste
6300ESB ICH
Yes
Yes
Yes
No
No
No
No
No
November 2007
r
Intel
as
Targe
®
Yes
Yes
Yes
Yes
No
No
No
No
t