NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 533

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

12—Intel
12.1.14 Offset 40h: HOSTC—Host Configuration Register
12.2
Table 439. SMB I/O Registers (Sheet 1 of 2)
November 2007
Order Number: 300641-004US
Bits
Default Value:
7:3
2
1
0
Table 438. Offset 40h: HOSTC—Host Configuration Register (SMBUS—D31:F3)
Device:
®
Offset:
HST_EN: SMBus Host
6300ESB ICH
SMB_SMI_EN
(SMBUS—D31:F3)
SMBUS I/O Registers
Reserved
Offset
I
Enable
31
40h
00h
Name
2
0Dh
0Bh
0Ch
00h
02h
03h
04h
05h
06h
07h
08h
09h
0A-
C_EN
HOST_BLOCK_DB
XMIT_SLVA
Mnemonic
RCV_SLVA
SLV_DATA
HST_CMD
HST_CNT
AUX_STS
HST_STS
AUX_CTL
HST_D0
HST_D1
PEC
Reserved.
0 = SMBus behavior.
1 = The Intel
0 = SMBus interrupts will not generate an SMI#.
1 = Any source of an SMB interrupt will instead be routed to
0 = Disable the SMBus Host Controller.
1 = Enable. The SMB Host Controller interface is enabled to
I
commands.
generate an SMI#. Refer to
SMI#”.
execute commands. The INTREN bit must be enabled for
the SMB Host Controller to interrupt or SMI#. The SMB
Host Controller will not respond to any new requests until
all interrupt requests have been cleared.
This bit needs to be set for SMBALERT# to be enabled.
2
C devices. This will change the formatting of some
Host Status
Host Control
Host Command
Transmit Slave Address
Host Data 0
Host Data 1
Host Block Data Byte
Packet Error Check
Receive Slave Address
Slave Data
Auxiliary Status
Auxiliary Control
Register Name/Function
®
6300ESB ICH is enabled to communicate with
Description
Attribute:
Function:
Size:
Section 5.19.5, “Interrupts/
3
Read/Write
8-bit
Default
0000h
00h
00h
00h
00h
00h
00h
00h
00h
44h
00h
00h
Intel
®
6300ESB I/O Controller Hub
Access
R/WC
R/WC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
533
DS