NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 596

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

14.2.3
14.2.4
Intel
DS
596
15:5
Bits
Bits
Default Value:
Default Value:
7:5
4:0
I/O Address:
I/O Address:
4
3
®
Table 520. x_LVI—Last Valid Index Register
Table 521. x_SR—Status Register (Sheet 1 of 2)
6300ESB I/O Controller Hub
Lockable:
Lockable:
Note: Software may read the registers at offsets 04h, 05h and 06h simultaneously by
Note: Software may read the registers at offsets 04h, 05h and 06h simultaneously by
Device:
Device:
Interrupt Status (BCIS)
Last Valid Index [4:0]
FIFO error (FIFOE)
Buffer Completion
Hardwired to 0
x_LVI—Last Valid Index Register
performing a single, 32-bit read from address offset 04h. Software may also read this
register individually by doing a single, 8-bit read to offset 05h. Reads across dWord
boundaries are not supported.
x_SR—Status Register
performing a single, 32-bit read from address offset 04h. Software may also read this
register individually by doing a single, 16-bit read to offset 06h. Reads across dWord
boundaries are not supported.
Reserved
29
MBAR + 05h (MILVI),
MBAR + 15h (MOLVI)
00h
No
Name
29
MBAR + 06h (MISR),
MBAR + 16h (MOSR)
0001h
No
Name
Hardwired to 0.
These bits indicate the last valid descriptor in the list. This
value is updated by the software as it prepares new buffers
and adds to the list.
Reserved.
0 = Cleared by writing a ‘1’ to this bit position.
1 = FIFO error occurs.
Modem in: FIFO error indicates a FIFO overrun. The FIFO
pointers don't increment, the incoming data is not written
into the FIFO, thereby being lost.
Modem out: FIFO error indicates a FIFO underrun. The
sample transmitted in this case should be the last valid
sample.
The Intel
run or overrun occurs when there are more valid buffers to
process.
0 = Cleared by writing a ‘1’ to this bit position.
1 = Set by the hardware after the last sample of a buffer has
been processed, AND if the Interrupt on Completion
(IOC) bit is set in the command byte of the buffer
descriptor. Remains active until software clears bit.
®
6300ESB ICH will set the FIFOE bit if the under-
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
5
Read/Write
8-bit
Core
5
Read/Write Clear
16-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—14
November 2007
Access
Access
R/WC
R/WC
R/W