NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 471

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

10—Intel
Table 368. Offset C0 - C1h: USB_LEGKEY—USB Legacy Keyboard/ Mouse Control
November 2007
Order Number: 300641-004US
Bits
Default Value:
9
8
7
6
5
4
3
Device:
®
SMI on USB IRQ Enable
Offset:
SMI Caused by Port 60
SMI Caused by Port 60
A20Gate Pass-Through
SMI on Port 64 Writes
Enable (A20PASSEN)
6300ESB ICH
Write (TRAPBY60W)
SMI at End of Pass-
Pass-Through State
Read (TRAPBY60R)
Enable (64WEN)
through Enable
(SMIATENDPS)
(USBSMIEN)
Register (USB—D29:F0/F1) (Sheet 2 of 3)
(PSTATE)
29
C0-C1h
2000h
Name
Indicates if the event occurred. Note that even when the
corresponding enable bit is not set in the bit 1, this bit will
still be active. It is up to the SMM code to use the enable bit
to determine the exact cause of the SMI#. Note that the
A20Gate Pass-Through Logic allows specific port 64h writes to
complete without setting this bit.
0 = Software clears this bit by writing a ’1’ to the bit location
1 = Event Occurred.
NOTE: If bit 7 of the ETR1 (D31:F0, offset F4h ETR1) is set.
Indicates if the event occurred. Note that even when the
corresponding enable bit is not set in the bit 0, this bit will
still be active. It is up to the SMM code to use the enable bit
to determine the exact cause of the SMI#.
0 = Software clears this bit by writing a ’1’ to the bit location
1 = Event Occurred.
NOTE: If bit 7 of the ETR1 (D31:F0, offset F4h ETR1) is set.
May need to cause SMI at the end of a pass-through. May
occur when an SMI is generated in the middle of a pass
through and needs to be serviced later.
0 = Disable
1 = Enable
0 = When software needs to reset this bit, it should set bit 5
1 = Indicates that the state machine is in the middle of an
0 = Disable.
1 = Allows A20GATE sequence Pass-Through function. A
0 = Disable
1 = USB interrupt will cause an SMI event.
0 = Disable
1 = A ’1’ in bit 11 will cause an SMI event.
NOTE: If bit 7 of the ETR1 (D31:F0, offset F4h ETR1) is set.
in any of the controllers.
in any of the controllers.
in all of the host controllers to 0.
A20GATE pass-through sequence.
specific cycle sequence involving writes to port 60h and
64h does not result in the setting of the SMI status bits.
See
Extended Features Register (LPC I/F—D31:F0)”
more information. Port 60 Writes initiated from an
external PCI agent will not set this bit.
See
Extended Features Register (LPC I/F—D31:F0)”
more information. Port 60 Reads initiated from an
external PCI agent will not set this bit.
See
Extended Features Register (LPC I/F—D31:F0)”
more information. Port 64 Writes initiated from an
external PCI agent will not set this bit.
Section 8.1.37, “Offset F4: ETR1—PCI-X
Section 8.1.37, “Offset F4: ETR1—PCI-X
Section 8.1.37, “Offset F4: ETR1—PCI-X
Description
Attribute:
Function:
Size:
0/1
Read/Write
16-bit
Intel
®
6300ESB I/O Controller Hub
for
for
for
Access
R/WC
R/WC
R/W
R/W
R/W
R/W
RO
471
DS