NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 552

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

13.1.3
13.1.4
Intel
DS
552
15:1
Bits
Default Value:
0
9
8
7
6
5
4
3
2
1
®
Table 462. Offset 04 - 05h: PCICMD—PCI Command Register (Audio—D31:F5)
6300ESB I/O Controller Hub
Lockable:
Note: PCICMD is a 16-bit control register. Refer to the PCI 2.2 specification for complete
Note: PCISTS is a 16-bit status register. Refer to the PCI 2.2 specification for complete details
Note: When a master abort occurs on a memory read request performed by a particular
Device:
Invalidate Enable (MWI)
Offset:
Memory Space Enable
Parity Error Response
SERR# Enable (SEN)
Special Cycle Enable
VGA Palette Snoop
Memory Write and
Bus Master Enable
Fast Back-to-Back
Wait Cycle Control
Enable (FBE)
Offset 04 - 05h: PCICMD—PCI Command Register
(Audio—D31:F5)
details on each bit.
Offset 06 - 07h: PCISTS—PCI Device Status
Register (Audio—D31:F5)
on each bit.
channel, the run bit for that channel gets cleared immediately, and the corresponding
DMA engine halts. Write requests are posted and hence aborts cannot be seen by the
Intel
Reserved
(WCC)
31
04-05h
0000h
No
Name
(BME)
(MSE)
(PER)
(VPS)
(SCE)
®
6300ESB ICH AC’97 controller for write requests.
Reserved. Read ‘0’.
Not implemented. Hardwired to ‘0’.
Not implemented. Hardwired to ‘0’.
Not implemented. Hardwired to ‘0’.
Not implemented. Hardwired to ‘0’.
Not implemented. Hardwired to ‘0’.
Not implemented. Hardwired to ‘0’.
Not implemented. Hardwired to ‘0’.
Controls standard PCI bus mastering capabilities.
0 = Disable.
1 = Enable
Enables memory space addresses to the AC’97 Audio
Controller.
Power Well:
Description
Attribute:
Function:
Size:
5
Read/Write
16-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—13
November 2007
Access
R/W
R/W