NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 642

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 576. IRQPA—IRQ Pin Assertion Register
17.2.5
Table 577. EOIR—EOI Register
Intel
DS
642
31:5
31:8
Bits
Bits
Default Value:
Default Value:
4:0
7:0
®
6300ESB I/O Controller Hub
Address:
Address:
Memory
Note: When there are multiple I/O Redirection entries, assign the same vector for more than
Memory
Device:
Device:
End of Interrupt (EOI)
IRQ Number
EOIR—EOI Register
The EOI register is present to provide a mechanism to maintain the level-triggered
semantics for level-triggered interrupts issued on the parallel bus.
When a write is issued to this register, the I/O APIC will check the lower 8 bits written
to this register and compare them with the vector field for each entry in the I/O
Redirection Table. When a match is found, the Remote_IRR bit for that I/O Redirection
Entry will be cleared.
one interrupt input. Each of those entries will have the Remote_IRR bit reset to ‘0’. The
interrupt that was prematurely reset will not be lost because if its input remained active
when the Remote_IRR bit is cleared, the interrupt will be reissued and serviced at a
later time. Only bits 7:0 are actually used. Bits 31:8 are ignored.
Reserved
Reserved
29
FEC0_0020h
N/A
Name
29
FEC0_0040h
N/A
Name
Reserved. To provide for future expansion, the processor
should always write a value of ’0’ to Bits 31:5.
Bits 4:0 written to this register contain the IRQ number for
this interrupt. The only valid values are 0-23.
Reserved. To provide for future expansion, the processor
should always write a value of ’0’ to Bits 31:8.
Vector to be compared with vector field in the I/O redirection
table when an EOI is issued.
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
5
Write-Only
32-bit
5
Write-Only
32-bit
Order Number: 300641-004US
Intel
®
6300ESB ICH—17
November 2007
Access
Access
WO
WO