NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 595

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

14—Intel
14.2.1
14.2.2
November 2007
Order Number: 300641-004US
31:3
Bits
Bits
Default Value:
Default Value:
2:0
7:5
4:0
I/O Address:
I/O Address:
Table 518. x_BDBAR—Buffer Descriptor List Base Address Register
Table 519. x_CIV—Current Index Value Register
Lockable:
Lockable:
Note: Software may read the register at offset 00h by performing a single 32-bit read from
Note: Software may read the registers at offsets 04h, 05h and 06h simultaneously by
Device:
Device:
®
Buffer Descriptor List
6300ESB ICH
Current Index Value
Base Address[31:3]
x_BDBAR—Buffer Descriptor List Base Address
Register
address offset 00h. Reads across dWord boundaries are not supported.
x_CIV—Current Index Value Register
performing a single 32-bit read from address offset 04h. Software may also read this
register individually by doing a single 8-bit read to offset 04h. Reads across dWord
boundaries are not supported.
29
MBAR + 00h (MIBDBAR),
MBAR + 10h (MOBDBAR)
00000000h
No
Name
29
MBAR + 04h (MICIV),
MBAR + 14h (MOCIV)
00h
No
Name
[4:0]
These bits represent address bits 31:3. The entries should be
aligned on 8-byte boundaries.
Hardwired to ‘0’.
Hardwired to ‘0’.
These bits represent which buffer descriptor within the list of
16 descriptors is being processed currently. As each
descriptor is processed, this value is incremented.
Power Well:
Power Well:
Description
Description
Attribute:
Attribute:
Function:
Function:
Size:
Size:
5
Read/Write
32-bit
Core
5
Read-Only
8-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
Access
R/W
RO
595
DS