NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 381

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8—Intel
8.7
8.7.1
Table 266. NMI_SC—NMI Status and Control Register
I
November 2007
Order Number: 300641-004US
Bits
Default Value:
7
6
5
4
3
2
1
0
Lockable:
®
Device:
SPKR_DAT_EN: Speaker
Offset:
TMR2_OUT_STS: Timer
6300ESB ICH
REF_TOGGLE: Refresh
Counter 2 OUT Status
TIM_CNT2_EN: Timer
IOCHK# NMI Source
IOCHK# NMI Enable
SERR# NMI Source
PCI_SERR_EN: PCI
SERR#_NMI_STS:
IOCHK_NMI_STS:
Counter 2 Enable
IOCHK_NMI_EN:
SERR# Enable
Cycle Toggle
Data Enable
CPU Interface Registers
NMI_SC—NMI Status and Control Register
31
61h
00h
No
Name
Status
Status
1 = PCI agent detected a system error and pulses the PCI
1 = An ISA agent (through SERIRQ) asserted IOCHK# on the
This bit reflects the current state of the 8254 counter 2
output. Counter 2 must be programmed following any PCI
reset for this bit to have a determinate value. When writing to
port 61h, this bit must be a 0.
This signal toggles from either 0 to 1 or 1 to 0 at a rate that is
equivalent to when refresh cycles would occur. When writing
to port 61h, this bit must be a 0.
0 = Enabled.
1 = Disabled and cleared.
0 = SERR# NMIs are enabled.
1 = SERR# NMIs are disabled and cleared.
0 = SPKR output is a 0.
1 = SPKR output is equivalent to the Counter 2 OUT signal
0 = Disable
1 = Enable
SERR# line. This interrupt source is enabled by setting bit
2 to 0. To reset the interrupt, set bit 2 to 1 and then set it
to 0. When writing to port 61h, this bit must be 0.
ISA bus. This interrupt source is enabled by setting bit 3
to 0. To reset the interrupt, set bit 3 to 0 and then set it
to 1. When writing to port 61h, this bit must be a 0.
value.
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write, Read-Only
8-bit
Core
Intel
®
6300ESB I/O Controller Hub
Access
R/W
R/W
R/W
R/W
RO
RO
RO
RO
381
DS