NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 128

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 50.
Intel
DS
128
®
6300ESB I/O Controller Hub
Short Message
Short messages are used for the delivery of Fixed, NMI, SMI, Reset, ExtINT and Lowest
Priority with Focus processor interrupts. The Delivery Mode bits (M2–M0) specify the
message. All short messages take 21 cycles including the idle cycle.
Short Message
NOTES:
1. When DM is 0 (physical mode), cycles 15 and 16 are the APIC ID and cycles 13 and 14 are
2. The checksum field is the cumulative add (mod 4) of all data bits (DM, M0-3, L, TM, V0-7,D0-
3. This cycle allows all APICs to perform various internal computations based on the information
Cycle
2 - 5
10
11
12
13
14
15
16
17
18
19
20
21
sent as ‘1’. When DM is 1 (logical mode), cycles 13 through 16 are the 8-bit Destination field.
The interpretation of the logical mode 8-bit Destination field is performed by the local units
using the Destination Format Register. Shorthands of “all-incl-self” and “all-excl-self” both
use physical destination mode and a destination field containing APIC ID value of all ones.
The sending APIC knows whether it should (incl) or should not (excl) respond to its own
message.
7). The APIC driving the message provides this checksum. This, in essence, is the lower two
bits of an adder at the end of the message.
contained in the received message. One of the computations takes the checksum of the data
received in cycles 6 through 16 and compares it with the value in cycle 18. When any APIC
computes a different checksum than the one passed in cycle 17, the APIC will signal an error
on the APIC bus (“00”) in cycle 19. When this occurs, all APICs will assume the message was
never sent and the sender must try sending the message again, which includes re-arbitrating
for the APIC bus. In lowest priority delivery when the interrupt has a focus processor, the
focus processor will signal this by driving a “01” during cycle 19. This tells all the other APICs
that the interrupt has been accepted, the arbitration is preempted, and short message format
is used. Cycle 19 and 20 indicates the status of the message, i.e., accepted, check sum error,
retry or error. The following table shows the status signal combinations and their meanings
for all delivery modes.
1
6
7
8
9
NOT(DM)
NOT(M1)
NOT(D7)
NOT(D5)
NOT(D3)
NOT(D1)
NOT(V7)
NOT(V5)
NOT(V3)
NOT(V1)
NOT(C1)
NOT(A1)
NOT(A)
NOT(L)
ARBID
Bit 1
1
1
1
NOT(M2)
NOT(M0)
NOT(TM)
NOT(V6)
NOT(V4)
NOT(V2)
NOT(V0)
NOT(D6)
NOT(D4)
NOT(D2)
NOT(D0)
NOT(C0)
NOT(A1)
NOT(A)
Bit 0
0
1
1
1
Normal Arbitration
Arbitration ID
DM
table register
M2-M0 = Delivery Mode from bits 10:8 of the
redirection table register
L = Level, TM = Trigger Mode
Interrupt vector bits V7 - V0 from redirection table
register
Destination field from bits 63:56 of redirection table
register
Checksum for Cycles 6 - 16
Postamble
Status Cycle 0. See
Status Cycle 1. See
Idle
1
= Destination Mode from bit 11 of the redirection
1
3
Table
Table
Comments
51.
51.
2
Order Number: 300641-004US
Intel
®
6300ESB ICH—5
November 2007