NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 340

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.1.33
Table 213. Offset ECh - EDh: GEN2_DEC—LPC I/F Generic Decode Range 2 (LPC I/
Intel
DS
340
15:4
Bits
Default Value:
3:1
0
®
6300ESB I/O Controller Hub
Lockable:
Device:
Offset:
GEN2_BASE
Offset ECh - EDh: GEN2_DEC—LPC I/F Generic
Decode
Range 2 (LPC I/F—D31:F0)
F—D31:F0)
GEN2_EN
Reserved
31
ECh - EDh
00h
Yes
Name
Generic I/O Decode Range 2 Base Address. This address is
aligned on a 64-byte boundary, and must have address lines
31:16 as 0.
Note that this generic decode is for I/O addresses only, not
memory addresses. The size of this range is 16 bytes.
Reserved. Read as 0.
Generic I/O Decode Range 2 Enable
0 = Disable.
1 = Accesses to the GEN2 I/O range will be forwarded to the
LPC I/F.
Power Well:
Description
Attribute:
Function:
Size:
0
Read/Write
16-bit
Core
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/W
R/W