NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 430

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

8.10.6
Table 318. Offset GPIOBASE + 2Ch: GPI_INV—GPIO Signal Invert Register
Intel
DS
430
31:1
10:9
13:1
Bits
1, 8
Default Value:
7:0
4,
®
6300ESB I/O Controller Hub
Lockable:
Device:
Offset:
GP_INV[n]
GP_INV[n]
Offset GPIOBASE + 2Ch: GPI_INV—GPIO Signal
Invert Register
Reserved
31
GPIOBASE +2Ch
00000000h
No
Name
Reserved.
These bits are used to allow both active-low and active-high
inputs to cause SMI# or SCI. Note that in the S0 or S1 state,
the input signal must be active for at least 2 PCI clocks to
ensure detection by the Intel
S5 states the input signal must be active for at least 2 RTC
clocks to ensure detection. The setting of these bits will have
no effect when the corresponding GPIO is programmed as an
output. These bits correspond to GPIO that are in the Resume
well, and will be reset to their default values by RSMRST# or
a write to the CF9h register.
0 = The corresponding GPIn_STS bit will be set when the
1 = The corresponding GPIn_STS bit will be set when the
NOTE: The GPIn_STS bits are in the GPE0_STS Register. See
These bits are used to allow both active-low and active-high
inputs to cause SMI# or SCI. Note that in the S0 or S1 state,
the input signal must be active for at least 2 PCI clocks to
ensure detection by the Intel
these bits will have no effect when the corresponding GPIO is
programmed as an output. These bits correspond to GPIO
that are in the Core well, and will be reset to their default
values by PXPCIRST#.
0 = The corresponding GPIn_STS bit will be set when the
1 = The corresponding GPIn_STS bit will be set when the
Intel
be high.
Intel
be low.
Intel
be high.
Intel
be low.
section 9.8.3.7
®
®
®
®
6300ESB ICH detects the state of the input pin to
6300ESB ICH detects the state of the input pin to
6300ESB ICH detects the state of the input pin to
6300ESB ICH detects the state of the input pin to
Power Well:
Description
Attribute:
Function:
®
®
Size:
6300ESB ICH. In the S3, S4 or
6300ESB ICH. The setting of
0
Read/Write
32-bit
See bit description
Order Number: 300641-004US
Intel
®
6300ESB ICH—8
November 2007
Access
R/W
R/W