NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 167

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

5—Intel
5.11.11.4Controlling Leakage and Power Consumption during Low-
5.11.12 Clock Generators
Table 77.
November 2007
Order Number: 300641-004US
AC_BIT_CLK
PXPCICLK
Domain
PCICLK
CLK66
CLK48
CLK14
Clock
®
6300ESB ICH
Power States
To control leakage in the system, various signals will tri-state or go low during some
low-power states.
General principles:
Based on the above principles, the following measures are taken:
The clock generator is expected to provide the frequencies shown in
Intel
•
•
•
•
14.318 MHz
12.288 MHz
Frequency
All signals going to powered down planes (either internally or externally) must be
either tri-stated or driven low.
Signals with pull-up resistors should not be low during low-power states. This is to
avoid the power consumed in the pull-up resistor.
Buses should be halted (and held) in a known state to avoid a floating input
(perhaps to some other device). Floating inputs may cause extra power
consumption.
During S3 (STR), all signals attached to powered down planes will be tri-stated or
driven low.
66 MHz
33 MHz
66 MHz
48 MHz
®
6300ESB ICH Clock Inputs
Main Clock Generator
Main Clock Generator
Main Clock Generator
Main Clock Generator
Main Clock Generator
AC’97 Codec
Source
Clock for Hub Interface. Should be running in all
Cx states. Stopped in S3 ~ S5 based on SLP_S3#
assertion. This signal is not 5V tolerant.
Free-running PCI Clock to the Intel
ICH. Provides timing for all transactions on the
internal primary PCI bus, as well as units inside
the Intel
This clock may be stopped in S3, S3 or S5 states.
This signal is not 5V tolerant.
Free-running PCI Clock to the Intel
ICH. Provides timing for all transactions on the
internal primary PCI-X bus, as well as units inside
the Intel
This clock may be stopped in S3, S3 or S5 states.
This signal is not 5V tolerant.
Used by USB Controllers. Stopped in S3 ~ S5
based on SLP_S3# assertion.
Used by ACPI timers. Stopped in S3 ~ S5 based
on SLP_S3# assertion.
AC’97 Bit Clock: 12.288 MHz serial data clock
generated by the external CODECs. Integrated
pull down resistor.
®
®
6300ESB ICH.
6300ESB ICH.
Description
Intel
®
6300ESB I/O Controller Hub
Table
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®
6300ESB
6300ESB
77.
167
DS