NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 660

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

18.6.1.8 Offset 0D: PLT—Primary Latency Timer
18.6.1.9 Offset 0E: HTYPE—Header Type
Intel
DS
660
07:0
02:0
06:0
Bits
Bits
07
3
®
Table 591. Offset 0D: PLT—Primary Latency Timer
Table 592. Offset 0E: HTYPE—Header Type
6300ESB I/O Controller Hub
Note: This register does not apply to Hub Interface and is maintained as R/W for software
Note: This register determines how the rest of the configuration space is laid out.
Time Value
Device
Device
Offset
Reserved
Offset
(HTYPE)
function
Header
Name
Name
device
(MFD)
Multi-
(TV)
Type
compatibility.
28
0D
28
0E
Read/write for software compatibility only.
Reserved.
Reserved as ’0’ to indicate the bridge is a single function
device.
Defines the layout of addresses 10h through 3Fh in
configuration space. Reads as ‘01h’ to indicate that the
register layout conforms to the standard PCI-to-PCI bridge
layout.
Description
Description
Attribute:
Attribute:
Function
Function
Size:
Size:
0
Read/Write
8-bit
0
Read-Only
8-bit
Order Number: 300641-004US
Reset
Value
Reset
Value
00h
000
01h
Intel
0
®
6300ESB ICH—18
November 2007
Access
Access
R/W
RO
RO
RO