NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 476

• Manufacturer Part Number: NHE6300ESB S L7XJ
• Manufacturer: Intel

Specifications of NHE6300ESB S L7XJ

• Lead Free Status / RoHS Status: Compliant

Table 371. Offset 00 - 01h: USBCMD—USB Command Register (Sheet 3 of 3)
Intel
DS
476
Bits
Default Value:
2
1
0
®
6300ESB I/O Controller Hub
Device:
Offset:
Global Reset (GRESET)
Host Controller Reset
Run/Stop (RS)
(HCRESET)
29
00-01h
0000h
Name
0 = This bit is reset by the software after a minimum of 10
1 = Global Reset. The Host Controller sends the global reset
The effects of HCRESET on Hub registers are slightly different
from Chip Hardware Reset and Global USB Reset. The
HCRESET affects bits [8,3:0] of the Port Status and Control
Register (PORTSC) of each port. HCRESET resets the state
machines of the Host Controller including the Connect/
Disconnect state machine (one for each port). When the
Connect/Disconnect state machine is reset, the output that
signals connect/disconnect are negated to 0, effectively
signaling a disconnect, even if a device is attached to the
port. This virtual disconnect causes the port to be disabled.
This disconnect and disabling of the port causes bit 1
(connect status change) and bit 3 (port enable/disable
change) of the PORTSC to get set. The disconnect also causes
bit 8 of PORTSC to reset. About 64 bit times after HCRESET
goes to ‘0’, the connect and low-speed detect will take place,
and bits 0 and 8 of the PORTSC will change accordingly.
0 = Reset by the Host Controller when the reset process is
1 = Reset. When this bit is set, the Host Controller module
When set to ‘1’, the Intel
execution of the schedule. The Intel
execution as long as this bit is set. When this bit is cleared,
the Intel
the USB and then halts. The HC Halted bit in the status
register indicates when the Host Controller has finished the
transaction and has entered the stopped state. The Host
Controller clears this bit when the following fatal errors occur:
consistency check failure, PCI Bus errors.
0 = Stop
1 = Run
NOTE: This bit should only be cleared when there are no
ms has elapsed as specified in Chapter 7 of the USB
Specification.
signal on the USB and then resets all its logic, including
the internal hub registers. The hub registers are reset to
their power on state. Chip Hardware Reset has the same
effect as Global Reset (bit 2), except that the Host
Controller does not send the Global Reset on USB.
complete.
resets its internal timers, counters, state machines, etc.
to their initial value. Any transaction currently in progress
on USB is immediately terminated.
active Transaction Descriptors in the executable
schedule or software will reset the host controller
prior to setting this bit again.
®
6300ESB ICH completes the current transaction on
Description
®
Attribute:
Function:
6300ESB ICH proceeds with
Size:
®
0/1
Read/Write
16-bit
6300ESB ICH continues
Order Number: 300641-004US
Intel
®
6300ESB ICH—10
November 2007
Access
R/W
R/W
R/W