NHE6300ESB S L7XJ Intel, NHE6300ESB S L7XJ Datasheet - Page 791
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NHE6300ESB S L7XJ
Manufacturer Part Number
NHE6300ESB S L7XJ
Description
Manufacturer
Intel
Datasheet
1.NHE6300ESB_S_L7XJ.pdf
(848 pages)
Specifications of NHE6300ESB S L7XJ
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22—Intel
Table 709. DC Characteristic Input Signal Association (Sheet 2 of 2)
Table 710. DC Input Characteristics (Sheet 1 of 2)
November 2007
Order Number: 300641-004US
NOTES:
VTHRAVG/VRING
V
1. Applies to Ultra DMA Modes greater than Ultra DMA Mode 4.
2. This is an AC Characteristic that represents transient values for these signals.
3. V
4. Includes V
5. Applies to High-speed USB 2.0.
6. SATA Vdiff,rx is measured at the SATA connector on the receive side.
7. When probed at the receiver pin of the ICH for data/strobe, the waveform may show a “knee” due to package
Symbol
V
HSSQ
V+/V-/VHYS/
(5V Tolerant)
(5V Tolerant)
DI
parasitics. Simulation verifies that this “knee” represents no risk, since a clean waveform is present at the
ICH ball input due to internal receiver termination.
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DI
Symbol
IL10
IL11
IL12
IH0
IH1
IH2
IH3
IH4
IH5
IH6
IH7
IH8
IL0
IL1
IL2
IL3
IL4
IL5
IL6
IL7
IL8
/ V
IL9
V
/ V
= | USBPx[P] - USBPx[N].
HSCM
®
/V
/V
/V
/V
CM
6300ESB ICH
HSDSC
IH9
IH10
IH11
IH12
/ V
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
DI
SE
range.
/
SATA Signals: SATA[1:0]RX[P,N]
USB Signals: OC[3:0]#
AC’97 Signals: AC_BITCLK, AC_SDIN[2:0]
Clock Signals: SATACLKP, SATACLKN (CLK100P, CLK100N)
IDE Signals: PDD[15:0], SDD[15:0], PDDREQ, PIORDY, SDDREQ, SIORDY
For Ultra DMA Mode 4 and lower these signals, follow the DC characteristics for
V
USB Signals: USBP[3:0][P,N] (Low-speed and Full-speed)
USB Signals: USBP[3:0][P,N] (in High-speed Mode)
IH2
/V
Parameter
IL2.
0.73(V_CPU_IO)
HIREF + 0.10
0.5Vcc3_3
0.5Vcc3_3
0.5Vcc3_3
Associated Signals
-0.15
0.40
Min
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.3
-0.5
2.0
2.1
2.0
VccSus3_3 + 0.5
0.58(V_CPU_IO)
Vcc3_3 + 0.5
Vcc3_3 + 0.5
Vcc3_3 + 0.5
HIREF - 0.10
V5REF + 0.5
V5REF + 0.5
0.35Vcc3_3
0.3Vcc3_3
0.3Vcc3_3
V_CPU_IO
Max
0.10
0.8
0.8
0.8
1.2
1.0
Intel
®
6300ESB I/O Controller Hub
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Note 7
Note 7
Notes
791
DS
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